Intel Corporation

Lsi Logic Corporation

Daniel R Bockelman

Emery O Sugasawara

James McNames

Robert Madge

Kevin Cota

W Robert Daasch

Yuan-Chuan Steven Chen

Md Asifur Rahman

Chris J Brookreson

Benjamin M Mauck

Louie Y Liu

Christopher John Brookreson

A method and an apparatus to detect over clocking of a processor are illustrated. The over clocking detector may detect as to whether the system clock of a microprocessor is over clocked and then generate an over clocking indicator. The over clocking indicator may be stored and accessed at a later time. The over clocking indicator may be retrieved through a test access port.

Over clocking detecting and permitting access to stored over clocking indicator in a power down state

A diagnostic tool for testing an integrated circuit device directs a beam of laser energy to stimulate at least a portion of the device. In one mode, electromagnetic waves from said device may be detected at the same time in response to the stimulation. A processor collects image data and determines as a function of the collected image data whether the device has a defect. Other embodiments are described and claimed.

Integrated circuit testing with laser stimulation and emission analysis

A method for testing integrated circuits, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by position designations. The recorded output for the integrated circuits is mathematically manipulated, and the recorded output for each of the integrated circuits is individually compared to the mathematically manipulated recorded output for the integrated circuits. Graded integrated circuits that have output that differs from the mathematically manipulated recorded output for the integrated circuits by more than a given amount are identified, and a classification is recorded in the wafer map for the graded integrated circuits, referenced by the position designations for the graded integrated circuits.

Statistical decision system

A method for testing integrated circuits having associated position designations, where a predetermined set of input vectors is introduced as test input into the integrated circuits. The output from the integrated circuits in response to the predetermined set of input vectors is sensed, and the output from the integrated circuits is recorded in a wafer map, referenced by the position designations. The output from at least a subset of the integrated circuits is selected and mathematically manipulated to produce a reference value. The output for each of the integrated circuits in the selected subset is individually compared to the reference value, and graded integrated circuits within the selected subset that have output that differs from the reference value by more than a given amount are identified. A classification is assigned to the graded integrated circuits and recorded in the wafer map, referenced by the position designations for the graded integrated circuits.

Test limits based on position

Growing community of inventors

Portland, OR, United States of America

Daniel R Bockelman