Sgs-thomson Microelectronics S.a.

Daniel Quessada

Jean Barret

Jacques Mille

A MOS-type vertical power transistor formed in a semiconductor layer having a bottom surface which constitutes a first electrode and a top surface, the transistor further includes a large number of identical cells that are connected in parallel with a second electrode and a control electrode formed on the top surface. The power transistor includes at least one additional cell, formed in the semiconductor layer, having the same shape as the identical cells but a smaller lateral size than the identical cells, and a circuit to turn on the power transistor when the additional cell reaches an avalanche mode.

Forward overvoltage protection circuit for a vertical semiconductor

An integrated circuit includes a vertical power transistor, a depletion-mode lateral MOS logic transistor and a lateral Schottky diode in an N.sup.+ epitaxial semiconductor layer of an N substrate. The depletion-mode lateral transistor and Schottky diode are in a P well formed in the epitaxial layer during a first doping step. The vertical power transistor and depletion-mode lateral transistor include P.sup.+ semiconductor regions formed during a second doping step. The lateral transistor and Schottky diode include an N doped semiconductor channel layer formed during a third doping step so they have similar characteristics. The vertical power transistor includes a P doped semiconductor channel layer formed during a fourth doping step. The lateral transistor, Schottky diode and channel of the vertical power transistor include N.sup.30 doped semiconductor regions formed during a fifth doping step. The semiconductor region formed during the fifth step associated with the Schottky diode forms a ring around the layer of the diode formed during the third step. Metal electrodes are formed on regions of the transistors and diode as formed during the fifth step and on the diode layer formed during the third step and on regions formed during the second step. The layer formed during the third step forms a junction about 0.7.mu. below the substrate and has a surface dopant concentration of about 10.sup.16 atoms/cm.sup.3.

VDMOS/logic integrated circuit comprising a diode

A resistor constituted by a spiral region (4) of a second conductivity type and having a determined doping level, formed on a first surface of a semiconductor substrate (1) of the first conductivity type, having a first terminal on the first surface of the substrate and a second terminal electrically connected to the opposite surface of the substrate through an overdoped region of the same conductivity type as the substrate, more conductive areas (11) being formed at determined places of the spiral.

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Pourrieres, France

Daniel Quessada