Bae Systems Information and Electronic Systems Integration Inc.

Ovonyx Inc.

Daniel Pirkl

Bin Li

Adam Matthew Bumgarner

Kenneth R Knowles

David D Moser

Neil Edward Wood

Patrick Fleming

George Michael

Andrew T Kelly

A ring oscillator circuit is disclosed. The ring oscillator in one embodiment includes an odd number of inverters connected in a loop fashion, a current mirror having a drain of a first transistor connected to the inverters, and a self-biased inverter connected to a drain of a second transistor of the current mirror.

Ring oscillator circuit with frequency stabilization

A system and method for controlling pulse width for electronic devices in real time is disclosed. The system includes a Digital Pulse Width Modulator (DPWM), a real time calibration circuit and a delay line circuit. The real time calibration circuit is configured to ensure proper fractional delay is applied to yield correct duty cycle of the DPWM. The delay line circuit comprising a multiplexer delay line with built in decoders, modulates the pulse width for fractional clock cycle delay.

Digitally controlled pulse width modulator utilizing real time calibration

A ring oscillator is disclosed. The ring oscillator includes a first tri-path inverter, a second tri-path inverter and a third tri-path inverter. The second tri-path inverter is connected to the first tri-path inverter. The third tri-path inverter is connected to the first and second tri-path inverters to provide feedback for oscillations.

Single-event upset hardened ring oscillator

An adjustable write pulse generator is disclosed. The adjustable write pulse generator includes a band-gap reference current, a programmable ring oscillator, a frequency divider and a single pulse generator. The band-gap reference current circuit generates a well-compensated current over a predetermined range of temperatures needed to program a chalcogenide memory cell. The programmable ring oscillator generates a first set of continuous write '0' and write '1' pulse signals based on the well-compensated current. The frequency divider then divides the first set of continuous write &#x201c;0&#x201d; and write &#x201c;1&#x201d; pulse signals into a second set of continuous write &#x201c;0&#x201d; and write &#x201c;1&#x201d; pulse signals. The single pulse generator subsequently converts the second set of continuous write &#x201c;0&#x201d; and write &#x201c;1&#x201d; pulse signals into a single write &#x201c;0&#x201d; pulse signal or a single write &#x201c;1&#x201d; pulse signal when programming the chalcogenide memory cell.

Adjustable write pulse generator within a chalcogenide memory device

A read reference circuit for a sense amplifier within a chalcogenide memory device is disclosed. The read reference circuit provides a reference voltage level to the sense amplifier for distinguishing between a logical '0' state and a logical '1' state within a chalcogenide memory cell. In conjunction with a precharge circuit, the read reference circuit generates a selectable read reference current to the sense amplifier in order to detect the logical state of the chalcogenide memory cell. The precharge circuit precharges the bitlines of the chalcogenide memory cell before the sense amplifier detects the logical state of the chalcogenide memory cell.

Growing community of inventors

Centreville, VA, United States of America

Daniel Pirkl