International Business Machines Corporation

Wafertech, Inc.

Daniel Piper

Jonathan R Fry

Yongchun Xin

Jang Sim

Ganesh Yerubandi

Franklin Chiang

Scott Westfall

A micro electrical mechanical system (MEMS) valve is provided. The MEMS valve includes first and second bodies, a medium and a thermal element. The first body defines a first channel and a second channel intersecting the first channel. The second body defines a third channel and is movable within the first channel between first and second positions. When the second body is at the first positions, the second and third channels align and permit flow through the second and third channels. When the second body is at the second positions, the second and third channels misalign and inhibit flow through the second channel. The medium is charged into the first channel at opposite sides of the second body. The thermal element is proximate to the first channel and is operable to cause the medium to drive movements of the second body to the first or the second positions.

Micro electrical mechanical system (MEMS) valve

Microfluidic chips incorporating liquid level sensors for precise sensing of liquid levels in microfluidic system structures, e.g., channels, cavities or reservoirs without moving parts. The microfluidic system uses liquid level photosensors and use optical properties to measure liquid volumes. A light coupling emitter or waveguide transmits the light toward the fluid channel at a critical angle. Multiple light coupling emitters and photosensor array can detect light for a variety of scenarios (based on fluid refraction index) and exploit the phenomenon of critical angles to measure exact angles of reflection/refraction. The waveguide coupler(s) and photosensors are manufactured at the microscale, and use both reflected light and refracted light as monitor signals. A feedback control system (e.g., compensating for rate and tolerance drift) is devised using signals generated by the sensors upon detecting reflected or refracted sensed light for increased accuracy of detecting precise amounts of fluid volumes being dispensed.

MEMS optical liquid level sensor

An optically readable chip ID is provided to an imprintable material that is formed as a last level of an integrated circuit (IC) chip using nanoimprint lithography. The nanoimprint lithography process provides an array of indentations into the imprintable material that is typically arranged in a hexadecimal pattern. The hexadecimal pattern includes one or more optically readable characters which combine to encode chip location identification data. The chip location identification data identifies a unique location of the product chip on a wafer prior to dicing.

Optical chip ID definition using nanoimprint lithography

A MEMS multiplexing system including: first and second fluid inputs; and a mixing network. The mixing network including: a first channel to receive the first fluid input; a second channel to receive the second fluid input; a multiplexing valve communicating with the first channel and the second channel, the multiplexing valve to cause the transport of the first fluid into the second channel so as to form a first interleaved fluid downstream from the multiplexing valve in the second channel and to cause the transport of the second fluid into the first channel so as to form a second interleaved fluid downstream from the multiplexing valve in the first channel; and the first channel and the second channel intersecting downstream from the valve so as to force mixing of the first interleaved fluid and the second interleaved fluid.

Micro electrical mechanical system (MEMS) multiplexing mixing

A self-cleaning sensor to determine a level of a liquid includes a tube with an interior coating and a plurality of horizontally aligned, electrically isolated, electrical contacts. The self-cleaning sensor includes the plurality of horizontally aligned, electrically isolated, electrical contacts that each terminate in an outer surface of an interior wall of the tube and are electrically connected to one or more electrical devices in a cap residing on the tube. Additionally, the self-cleaning sensor includes a float that is composed of a low density, low dielectric constant material buoyant in one or more liquids to be measured where each horizontal dimension of the float corresponds to each horizontal dimension of the tube.

Self-cleaning liquid level sensor

A micro electrical mechanical system (MEMS) optical sensor including a fluid channel having an input portion, an output portion and a curved portion positioned between the input portion and the output portion; a light source impinging on a first boundary of the curved portion and exiting from a second boundary of the curved channel; a photodetector to record a light path of refraction of the light source exiting from the second boundary of the curved portion; a processor to compute the refractive index of a fluid in the curved portion using the light path of refraction of the light source and compare the computed refractive index to a known refractive index for the fluid to determine a difference between the computed refractive index and the known refractive index.

MEMS optical sensor

Embodiments of the invention are directed to a method and resulting structures for forming optically readable chip identification (CID) codes using dummy controlled collapse chip connection (C4) bumps. In a non-limiting embodiment of the invention, a product chip is formed on a wafer. A chip location identifier including a plurality of controlled collapse chip connection (C4) bumps is formed on a surface of the product chip. The chip location identifier encodes a unique location of the product chip on the wafer prior to dicing. The plurality of C4 bumps are arranged into one or more optically readable alphanumeric characters.

Optical electronic-chip identification writer using dummy C4 bumps

Provided is a test pattern structure for determining overlay accuracy in a semiconductor device. The test pattern structure includes one or more resistor structures formed by patterning a lower silicon layer. Each includes a zigzag portion with leads at different spatial locations. An upper pattern is formed and includes at least one pattern feature formed over the resistor or resistors. The portions of the resistor or resistors not covered by the upper pattern feature will become silicided during a subsequent silicidation process. Resistance is measured to determine overlay accuracy as the resistor structures are configured such that the resistance of the resistor structure is determined by the degree of silicidation of the resistor structure which is determined by the overlay accuracy between the upper and lower patterns.

Test structure for determining overlay accuracy in semiconductor devices using resistance measurement

Test structure and method for determining overlay accuracy in semiconductor devices using resistance measurement

A shallow trench isolation (STI) structure includes a top surface formed completely of silicon nitride. The top surface of the STI structure is coplanar with a top substrate surface or extends above the top substrate surface. The STI structures include further dielectric materials beneath the silicon nitride and an oxide liner and any portions that extend above the substrate surface are formed of silicon nitride.

Nitride shallow trench isolation (STI) structures

A vertically integrated semiconductor device includes multiple continuous single crystal silicon layers vertically separated from one another by a dielectric layer or layers. Semiconductor devices are disposed on an underlying single crystal silicon substrate and the continuous single crystal silicon layers. The individual devices are interconnected to one another using tungsten or doped polysilicon leads that extend through openings formed in the continuous single crystal silicon layers. The method for forming the structure includes forming a dielectric material over the single crystal silicon layer or substrate and forming an opening extending down to the surface of the single crystal silicon material to act as a seed layer. An epitaxial silicon growth process begins at the seed location and laterally overgrows the openings. Growth fronts from the various seed locations meet to form a continuous single crystal silicon layer which is then polished.

Vertical integrated semiconductor device with multiple continuous single crystal silicon layers vertically separated from one another

Method of fabricating vertical integrated semiconductor device with multiple continuous single crystal silicon layers vertically separated from one another

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Vancouver, WA, United States of America

Daniel Piper