Applied Materials, Inc.

Daniel Philippe Cellier

Ellie Y Yieh

Mehul B Naik

John Tolle

Seshadri Ramaswami

Vanessa Pena

Andrew Cockburn

Thomas Kirschenheiter

Wei Hong

Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).

Monolithic complementary field-effect transistors having carbon-doped release layers

Growing community of inventors

Wallonia, Belgium

Daniel Philippe Cellier