Agere Systems Inc.

Lucent Technologies Inc.

Qorvo Us, Inc.

Triquint Semiconductor Corporation

Daniel Patrick Chesire

Sailesh Mansinh Merchant

Taeho Kook

Seung Hyuk Kang

Mark Adam Bachman

Kurt George Steiner

Vance D Archer, Iii

Vivian Wanda Ryan

Vance Dolvan Archer

Warren K Gladden

Alan Sangone Chen

Benjamin P Abbott

Kouros Azimi

Joze E Antol

Philip William Seitzer

Timothy Scott Campbell

Kelly Hinckley

Rafe Carl Mengel

Curtiss Hella

Thomas B Gans

Chad Thompson

Gregory A Head

Benu B Patel

John William Osenbach

Leonard Jay Olmer

Donald Stephen Bitting

Michael C Ayukawa

Edward P Martin

Rafael N Barba

Barbara D Kotzias

Embodiments of a Surface Acoustic Wave (SAW) device, or filter, and methods of fabrication thereof are disclosed. In some embodiments, the SAW filter comprises a piezoelectric substrate and an Interdigitated Transducer (IDT) on a surface of the piezoelectric substrate. The IDT includes multiple fingers, each comprising a metal stack. The SAW filter further includes a cap layer on a surface of the IDT opposite the piezoelectric substrate and on areas of the surface of the piezoelectric substrate exposed by the IDT. The cap layer has a thickness in a range of and including 10 to 500 Angstroms and a high electrical resistivity (and thus a low electrical conductivity). For instance, in some embodiments, the electrical resistivity of the cap layer is greater than 10 kilo-ohm meters (K&#x3a9;&#xb7;m). The SAW filter further includes an oxide overcoat layer on a surface of the cap layer opposite the IDT and the piezoelectric substrate.

Surface acoustic wave filter with a cap layer for improved reliability

Embodiments described herein may provide a temperature-compensated surface acoustic wave (TCSAW) device, a method of fabricating a TCSAW device, and a system incorporating a TCSAW device. The TCSAW device may include a pyroelectric substrate, a plurality of electrodes formed on a first surface of the pyroelectric substrate, an amorphous silicon layer formed over the plurality of electrodes, and a temperature compensating layer formed over the amorphous silicon layer.

Methods, systems, and apparatuses for temperature compensated surface acoustic wave device

The present invention provides a solder bump structure. In one aspect, the solder bump structure is utilized in a semiconductor device, such as an integrated circuit. The semiconductor device comprises active devices located over a semiconductor substrate, interconnect layers comprising copper formed over the active devices, and an outermost metallization layer positioned over the interconnect layers. The outermost metallization layer comprises aluminum and includes at least one bond pad and at least one interconnect runner each electrically connected to an interconnect layer. An under bump metallization layer (UBM) is located over the bond pad, and a solder bump is located over the UBM.

Routing under bond pad for the replacement of an interconnect layer

The invention, in one aspect, provides a semiconductor device (), including transistors (), dielectric layers () located over the transistors (), interconnects () formed within the dielectric layers (), and a test structure () located adjacent a hot-spot () of the semiconductor device () and configured to monitor a real-time operational parameter of at least one of the transistors () or interconnects ().

Thermal monitoring and management of integrated circuits

A solder bump structure and an under bump metallurgical structure. An upper surface of a semiconductor substrate comprises a first conductive pad () disposed thereon. A passivation layer () overlies the upper surface. A second conductive pad () is disposed in an opening () in the passivation layer and in contact with the first conductive pad. The under bump metallurgical structure () encapsulates the second conductive pad, covering an upper surface and sidewalls surfaces of the second conductive pad, protecting both the first and the second conductive pads from environmental and processing effects. According to the present invention, the conventional second passivation layer is not required. Methods for forming the various structures are also presented.

Structure and method for fabricating flip chip devices

A process for etching a sacrificial layer of a structure. The structure is exposed to a plasma derived from nitrogen trifluoride for etching the sacrificial layer. The process is selective in that it etches titanium-nitride and titanium but does not affect adjacent silicon dioxide or aluminum layers. Applications of the process include the formation of integrated circuit structures and MEMS structures.

Selective isotropic etch for titanium-based materials

An integrated circuit device incorporating a metallurgical bond to enhance thermal conduction to a heat sink. In a semiconductor device, a surface of an integrated circuit die is metallurgically bonded to a surface of a heat sink. In an exemplary method of manufacturing the device, the upper surface of a package substrate includes an inner region and a peripheral region. The integrated circuit die is positioned over the substrate surface and a first surface of the integrated circuit die is placed in contact with the package substrate. A metallic layer is formed on a second opposing surface of the integrated circuit die. A preform is positioned on the metallic layer and a heat sink is positioned over the preform. A joint layer is formed with the preform, metallurgically bonding the heat sink to the second surface of the integrated circuit die.

Integrated circuit device incorporating metallurgical bond to enhance thermal conduction to a heat sink

Disclosed herein are novel damage detection circuitries implemented on the periphery of a semiconductor device. The circuitries disclosed herein enable the easy identification of cracks and deformation, and other types of damage that commonly occur during test and assembly processes of semiconductor devices.

Semiconductor with damage detection circuitry

An integrated circuit structure and a method for fabricating the structure. The method comprises forming a copper bond pad for attaching the integrated circuit to a package. Copper oxide is removed from the pad by reduction in a hydrogen ion atmosphere. For attaching the integrated circuit to a bump-bonding package an under-bump metallization layer is formed over the reduced copper pad and a solder bump formed thereover. The process can also be employed in a wire bonding process by forming an aluminum layer overlying the cleaned copper pad. The structure of the present invention comprises a copper pad formed in a substrate. A passivation layer defining an opening therein overlies the copper pad. A under-bump metallization layer is disposed in the opening and a solder bump overlies the metallization layer. Alternatively, the structure further comprises an aluminum pad disposed overlying the reduced copper pad.

Structure and method for bonding to copper interconnect structures

Integrated circuit device incorporating metallurigical bond to enhance thermal conduction to a heat sink

Disclosed herein are novel support structures for pad reinforcement in conjunction with new bond pad designs for semiconductor devices. The new bond pad designs avoid the problems associated with probe testing by providing a probe region that is separate from a wire bond region. Separating the probe regionfrom the wire bond regionand forming the bond padover active circuitry has several advantages. By separating the probe regionfrom the wire bond region, the wire bond regionis not damaged by probe testing, allowing for more reliable wire bonds. Also, forming the bond padover active circuitry, including metal interconnect layers, allows the integrated circuit to be smaller.

Reinforced bond pad for a semiconductor device

An interface assembly () and method for testing a semiconductor wafer prior to performing a flip chip bumping process are provided. The interface assembly includes a flip chip bonding pad () having a region () for performing the bumping process. A test pad () is integrally constructed with the bonding pad and includes a probe region () for performing wafer-level testing prior to performing the bumping process. The integral construction of the bonding and testing pads avoids, for example, an introduction of propagation delays to test signals passing therethrough, thereby improving the accuracy and reliability of wafer test results.

Method and structures for testing a semiconductor wafer prior to performing a flip chip bumping process

Disclosed herein is a reinforcing system and method for reinforcing a contact pad of an integrated circuit. Specifically exemplified is a system and method that comprises a reinforcing structure interposed between a top contact pad layer and an underlying metal layer.

Growing community of inventors

Orlando, FL, United States of America

Daniel Patrick Chesire