Advanced Micro Devices Corporation

Daniel Parrenas Shimizu

Sateesh Lagudu

Qi Chen

Ali Ibrahim

Ashwini Dwarakanath

Rex George

Chi-Shung David Wang

Niranjan P Dasiga

Sai Kishore Reddipalli

A new motion adaptive deinterlacing method and apparatus detects motion corresponding to a pixel to be interpolated. The method and apparatus generates a subframe level motion map based on at least a portion of a current field and at least a portion of a plurality of previous fields. Based on the generated subframe level motion map, the apparatus and method generates a plurality of motion vectors associated with the subframe level motion map by applying a plurality of motion masks, associated with the pixel to be interpolated, to the subframe level motion map. The apparatus and method further generates deinterlaced content by adaptively interpolating the pixel to be interpolated for the current field based on the plurality of motion vectors produced by applying a plurality of motion masks to the subframe level motion map.

Subframe level latency de-interlacing method and apparatus

An integrated circuit comprising a plurality of functional blocks, each functional block being operative to cause one or more power consuming events, each power consuming event being associated with a respective weight. The integrated circuit also comprises at least one accumulation block for monitoring the functional blocks over a time window and generating a weighted count of the number of occurrences of each power consuming event within the time window; and a power calculation module for calculating a runtime power consumption estimate over the time window using the weighted count. The weighted count may comprise a sum of products of each one of the power consuming events by its respective weight. Calculating the runtime power consumption estimate may comprise averaging the weighted count over the time window to generate a dynamic power estimate, calculating a leakage power estimate over the time window, and summing the dynamic power estimate with the leakage power estimate. The integrated circuit may further comprise a power management module for adapting power consumption of the integrated circuit based on a comparison of the runtime power consumption estimate with one or more predetermined thresholds.

Realtime power management of integrated circuits

Embodiments of a dynamic leakage control circuit for use with graphics processor circuitry are described. The dynamic leakage control circuit selectively enables back biasing of the transistors comprising the graphics processor circuits during particular modes of operation. The back biasing levels are controlled by two separate power rails. A first power rail is coupled to an existing power supply and the second power rail is coupled to a separate adjustable voltage regulator. A separate voltage regulator may also be provided for the first power rail. A hardware-based state machine or software process is programmed to detect the occurrence of one or more modes of operation and adjust the voltage regulators for the first and second power rails to either enable or disable the back biasing state of the circuit, or alter the threshold voltage of the circuit within a specified voltage range.

Dynamic leakage control using selective back-biasing

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Hillsborough, CA, United States of America

Daniel Parrenas Shimizu