Advanced Micro Devices Corporation

Other

Daniel P Mann

James Raymond Magro

Carl Kittredge Wakeland

David Francis Tobias

Gary Michael Godfrey

Floyd Goodrich, Iii

Andrew Cohen

Provided are methods and compositions for providing strength and/or rigidity to lightweight materials. In certain embodiments, provided are compositions and methods for providing strength, rigidity and/or improving performance of flotation devices such as surfboards.

Flotation devices

An apparatus and method for integrating the delivery of data from a multiplicity of sources to a set of user electronic devices that present audio, video and digital information to the user is implemented. These devices may include conventional television displays, personal computers, and other conventional audio and video equipment. Information may be received from a multiplicity of sources which may include may include digital television via terrestrial or satellite broadcast, terrestrial analog radio, and digital data exchanged via a public network, such as the Internet. The mechanism of the present invention receives the multiplicity of data streams, processes them in accordance with each stream's formatting protocols (whether an analog stream, an MPEG Transport Stream, or TCP/IP stream, for example), including any conditional access protocols, and streams the processed data, in multiplexed transport stream to the user's presentation devices via a 'fat' pipe, such as a FireWire&#x2122; bus. A thin client interface decodes the streamed data addressed to its corresponding presentation device.

Apparatus for delivery of multiple media data streams, and method therefor

The remotely accessible Integrated Debug Environment of this invention permits a user having only a computer and an Internet connection to remotely access an IDE configured for operating and debugging a selected target microprocessor or microcontroller. An IDE is set up, including a host computer which operates as a web server and as a target/debug controller. One or more target processors may be connected to the host computer, along with debug equipment, such as logic analyzers, ICE equipment, overlay memory, etc. The host computer includes toolsets that correspond to the available target processor(s). In order to execute or debug code on a selected target processor, a user connects to the host computer using a web browser, with which the user can determine the availability of target processors and other pertinent information. The user can then download user interface software that will enable the user to implement an appropriate user interface on his computer, using the Internet to communicate with the host computer. Once the user interface is set up, the remote user can use the IDE system as though he were a local user, using control techniques familiar to those skilled in the art, to execute or debug software on the target processor. In preferred embodiments, the user interface is transmitted to the user as a Java bytecode, which is executable on most general purpose personal computers and workstations using widely available Java interpreters.

Remotely accessible integrated debug environment

A microcontroller provides a register change summary resource for summarizing register changes. Selected system registers within each resource are coupled to bits in resource change registers of the register change summary resource using logic that tracks accesses to the system registers. Each resource change register is coupled to a bit in a summary register. For systems with numerous system registers, each summary register may be coupled to a bit in a higher-level summary register. The register change summary resource further provides a software-controlled bit mask register. A change in a summary or resource change register may trigger a processor interrupt. Each register in the register change summary resource can be reset, also under software control. The registers within the register change summary resource are accessible through a dedicated software development port.

Register change summary resource

An invalid configuration detection resource for identifying and reporting conflicts between system resources of a microcontroller or other device is provided. Selected system registers within each resource are monitored by discrete hardware logic within the invalid configuration detection resource. For each resource, a status register provides an encoding of the configuration for that resource. The invalid configuration detection resource then compares the status registers for invalid combinations, and encodes this information in a system status register. Alternatively, the invalid configuration detection resource monitors each selected system register, independent of the resource to which it belongs. Improper combinations of registers are then encoded in a system status register. An alternative embodiment uses software to replace the discrete hardware logic with a table that specifies invalid register combinations. The invalid configuration detection resource further provides a software-controlled bit mask register.

Invalid configuration detection resource

A communication protocol is implemented by a control bus using multi-purpose bi-directional signal lines. The bi-directional signal lines provide a single control path shared among any number of system devices. Tokens, defined by the combination of states of the bi-directional signal lines, are transmitted over the control bus to other system devices. A token can represent a number of control commands. A received token is decoded by a system device using decode logic into an appropriate control command associated with the token according to a predefined logic table. Since a token can represent a control command only originated target devices or a control command only originated by initiator devices, the control bus can support both types of control commands with fewer pincount and point-to-point connections than conventional unidirectional control signalling.

Multi-purpose bi-directional control bus for carrying tokens between initiator devices and target devices

A processor-based device supports performance optimization with use of an adaptive digital element. The adaptive digital element generates probability data corresponding to a probability of a performance parameter of the processor-based device. The probability data is repeatedly compared to input data corresponding to the performance parameter and is adapted to match the input data. After a predetermined number of samples, a probability value corresponding to the probability data and stored in a counter of the adaptive digital element converges to a good estimated probability of the performance parameter. The probability value is then detected and processed, and the processor-based device is adapted in accordance with the probability value. A processor of the processor-based device also can adapt system operation when the probability value reaches a predetermined trigger value. One advantage of this overall technique is that it essentially eliminates any prospect of counter overflow and associated interrupt processing. Also, the device can accommodate multiple performance parameters by selecting a particular performance parameter for measurement by the adaptive digital element.

Performance monitoring and optimization using an adaptive digital circuit

A host computer system is coupled to a target computer system in a computer system debug environment and accesses selected resources. A first function executed on the host, encodes a data structure with target resource descriptor information for at least one of the selected resources. A second function accesses the selected resources in accordance with the target resource descriptor information encoded in the data structure.

Apparatus and method for providing list and read list capability for a host computer system

A host computer system is coupled to a target computer system for operating in a debug environment. The host computer system includes a status register which can be interrogated. A programming interface encoded in computer readable media and executable on the host computer system, provides at least one callable function that determines whether a value of a selected bit or bits of the status register have changed from a predetermined state. The called function returns to a calling function in response to the change in value of the selected bit or bits. Otherwise, the called function waits for the change in value of the bit(s). The status register can include at least one status bit that indicates a state of the target computer system and a status bit that indicates a state of the host computer system.

Apparatus and method for providing a wait for status change capability for a host computer system

A computer system includes a memory for storing instructions executable by a processor and an on-chip trace memory having a plurality of locations for storing trace information that indicates execution flow in the processor. A trace access instruction provides for access to the on-chip trace memory on the processor. The trace access instruction can be a write instruction or a read instruction. Typically, both read and write to the trace memory is provided. The system also has the capability to trace on start or restart of an executable thread by providing to the processor an indication of which executable thread to trace via a debug port. That indicates to the processor to provide trace information when the executable thread starts. When execution of the executable thread starts, the processor places an identifier corresponding to the executable thread into the trace memory to indicate that subsequent entries placed into the trace memory are part of said executable thread. The processor may also provide an entry indicating when the thread stops executing.

Processor having a trace access instruction to access on-chip trace memory

An integrated circuit includes a performance monitoring circuit which includes an adaptive adder circuit coupled to receive a first input signal indicative of a performance parameter of the integrated circuit and to provide a count value as a measure of the probability of the performance parameter. The adaptive adder circuit includes a random number generator circuit providing a random number, a counter circuit providing a count value and a comparator circuit coupled to compare the random number and the count value and to output a compare signal indicative thereof, the compare signal being provided to the counter as an up/down count signal. The adaptive adder circuit also includes a first logic circuit coupled to receive the performance parameter being measured and the compare signal which outputs a first signal which is used for controlling operation of the counter circuit. The counter circuit is responsive to count up or down when the first input signal and the compare signal are at different values and the counter circuit does not count when the first input signal and the compare signal are at the same value.

Non-intrusive performance monitoring

A debugging environment maintains object information (e.g., object size) concurrently with data optimization operations by a write buffer of a target system. Within the target system, a system bus is coupled between a system memory and a microcontroller. A data optimization operation by the write buffer is detected by monitoring of a merge signal of the system bus by a bus monitoring device. When a data optimization operation is detected, data optimization attributes (e.g., object information, data and address) associated with the data optimization operation are captured in the form of an object information signal responsive to a capture signal from the bus monitoring device. The data optimization attributes may be stored in either a trace cache of the target system or a memory of external trace capture equipment connected to the debug port, or a memory of the bus monitoring device. In providing the data optimization attributes external to the microcontroller, the data optimization attribute may be temporarily held by trace pins of a debug port of the microcontroller. The data optimization attributes may be extracted from the object information signal and processed by the external trace capture equipment or the bus monitoring device. By processing the data optimization attributes, pre-optimization write object values may be reconstructed.

Maintaining object information concurrent with data optimization for debugging

A direct memory access engine supports multiple virtual direct memory access channels. The direct memory access engine includes a direct memory access controller and a parameter table in memory containing parameters for a plurality of virtual direct memory access channels. The controller engine provides a single physical direct memory access channel and a plurality of virtual direct memory access channels. One direct memory access channel of the plurality of virtual direct memory access channels may be active at a given time. The parameters for the active channel may be loaded from the parameter table to a physical direct memory access control block and a physical direct memory access channel resource of the direct memory access controller. The physical direct memory access control block of the direct memory access controller utilizes the physical direct memory access channel resource to perform a direct memory access transfer for the active channel based on the loaded parameters. The physical direct memory access channel resource is shared by the plurality of virtual direct memory access channels. The direct memory access engine further includes a direct memory access request line and a direct memory access acknowledge line for an active channel of the plurality of virtual direct memory access channels.

Direct memory access engine for supporting multiple virtual direct memory access channels

A processor-based device incorporating a software debug port that utilizes a JTAG or similar standardized interface, thereby providing a software debug communication mechanism that does not require a special bond-out package. In one embodiment of the invention, only standard JTAG pins are used for communications between a host platform and a target system incorporating a target processor. In another embodiment of the invention, the software debug port of the target processor is augmented for higher-speed access via optional sideband signals. When used in conjunction with an on-chip trace cache, the software debug port provides trace information for reconstructing instruction execution flow on the processor and is also capable of examining register contents without halting processor operation. The software debug port alleviates many of the packaging and clock synchronization problems confronting existing debug solutions.

Software debug port for a microprocessor

A processor provides trace capability. Trace information can be provided over a communication port that is operable both as a trace port and as a parallel debug port. The trace port provides trace information indicating instruction execution flow in the processor core. The operation of the communication port as a trace port and as a parallel debug port is mutually exclusive. The parallel debug port provides for transmission of debug information between a debug host controller and the processor. The parallel debug port and the trace port physically share pins. Bus request and grant signals are provided between the parallel debug port and a debug host controller to ensure that collisions do not occur between use by the trace port and the debug host controller. A separate serial debug port is also provided which can be used to enable the parallel debug port.

Growing community of inventors

Austin, TX, United States of America

Daniel P Mann