International Business Machines Corporation

Sensormatic Electronics Corporation

Daniel P Fuoco

Dennis L Moeller

Jonathan H Raymond

Luis A Hernandez

Esmaeil Tashakori

Eric Mathisen

Mark William Kellogg

Christopher M Herring

Jorge E Lenta

Thomas F Berkey

Lawrence Robert Mills

Michael J DeLoye

This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.

Personal computer with processor reset control

This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.

Personal computer with alternate system controller

The present invention relates to a computer system and method of using the same in which add-on memory cards are provided which have error correction code logic on the card and logic to do partial writes of data words. The system has a central processing unit (CPU), and a BUS interconnecting the CPU and the add-on memory cards which are configured to write data and read data from the add-on memory. The system is further configured (either within the CPU or as a separate function) to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory. The add-on memory has ECC logic to identify any byte having a single bit error in the data bytes or the parity bits written by the CPU to the add-on memory and to correct all single bit errors in data read from the add-on memory to the CPU.

Memory card, computer system and method of operation for differentiating

In a personal computing system the function of the DMA controllers in the 'AT' or 'ISA' bus has been modified so that the system may select whether the 16-bit DMA channels are to be used as 8-bit DMA channels or 16-bit DMA channels. An 8/16-bit mode bit for each of the 16-bit DMA channels is written in a control register during the system Power On Self Test routine. Once the mode bit is written for each of the three 16-bit DMA channels, it may be read when the channel is active to select whether the channel is to operate as an 8-bit or 16-bit channel. With this mode bit information available, the page addressing may be selectively changed from 128k size pages to 64k size pages when a 16-bit DMA channel is to be converted to 8-bit. In addition, the byte addressing within a page may be changed from two byte addressing during 16-bit mode to single byte addressing during 8-bit mode.

Selectable 8/16 bit DMA channels for 'ISA' bus

The present invention provides a computer system and method of using the same. Add-on memory cards for the system are provided which cards have error correction code logic on the card, and logic to do partial writes of data words. The system has a central processing unit (CPU), a BUS interconnecting the CPU and the add-on memory cards. The CPU or associated components are configured to write data and read data from the add-on memory as several data bytes constituting data words. The system is further configured either within the CPU or as a separate function to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory. The system itself does not contain error correction code (ECC). The add-on memory has ECC logic to identify any byte having a single bit error in the data bytes or the parity bits written by the CPU to the add-on memory and to correct all single bit errors in data read from the add-on memory to the CPU. The error correcting code includes logic to generate parity bits in the data bytes written by the CPU to the add-on memory and logic to compare the parity bits written by the CPU with those generated by the error correcting code logic.

Error correction code on add-on cards for writing portions of data words

This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of 'master' devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.

Growing community of inventors

Boca Raton, FL, United States of America

Daniel P Fuoco