Burroughs, Inc.

Other

Daniel P Drogichen

Dana A Gryger

John E Legory

Disclosed is a synchronous clock regenerator for generating a clock signal which can be reliably used to strobe a binary serial data signal. The incoming raw clock signal is fed into a tapped delay line which generates multiple delayed versions of the raw clock signal. Upon detection of a framing transition on the incoming data signal, the raw clock signal and multiple delayed clock signals are latched. The latched values are used to address a read only memory (ROM), the ROM containing codes specifying which, if any, of the set including the raw clock signal and multiple delayed clock signals provides the optimum phase to strobe the incoming data signal. The code read from the ROM is decoded, latched and fed to a l-of-n selector circuit. Thereafter, and until the next framing transition occurs, each raw clock pulse received is replaced by the corresponding one of the set of that raw clock pulse and the generated delayed versions of that raw clock pulse as selected by the previously latched inputs to the l-of-n selector.

Synchronous clock regenerator for binary serial data signals

In a data processing system wherein a binary data message is protected by cyclic check codes, synchronization loss tolerance is incorporated by performing a binary transformation after encoding the message but prior to transmitting it or writing it to storage and by performing an inverse binary transformation upon receiving it or reading it from storage but prior to error checking. In one embodiment the transformation involves complementing a plurality of bits. In an alternate embodiment the transformation involves reversing the sequence of a plurality of contiguous bits.

Synchronization loss tolerant cyclic error checking method and apparatus

A device for use with a digital computer for storing standard software used by the computer and modifying the address portions of the standard software prior to transmission to the computer. The device includes a ROM package containing a ROM within which is stored a standard software subprogram written assuming it is stored at an absolute location in the computer's memory other than its actual location in the computer's memory system. Also included in the ROM package is a base register which can be loaded, under control of the operating system software, with an offset value reflecting the difference between the actual starting memory system location of the subprogram stored in the ROM and the assumed absolute starting location of the subprogram. Each ROM word includes an extra bit to indicate whether the corresponding data word contains an address requiring relocation. As a word is read out of ROM, a gating circuit tests whether an address relocation is required. If the test is positive, the gating circuit gates the value in the base register into one input of an adder located on the ROM package, the other input to the adder coming from the data word read out of the ROM. The resulting modified data word outputted from the adder is sent to the computer. If the ROM output does not indicate that a relocation is required, the gating circuit provides a zero input to the adder so that the adder output reflects the unmodified input from the ROM.

External data store memory device

Device for automatic modification of ROM contents by a system selected

An apparatus for use as part of a computer system's external memory for storing a subprogram used by the computer and modifying selected data words read from the apparatus prior to transmission to the computer. The apparatus includes an addressable read only memory (ROM) having a word size which is greater than the instruction word size used by the computer. The apparatus also includes a plurality of base registers which may be loaded under control of the computer's operating system program. The read only memory contains a softwave subprogram written assuming it is stored at an absolute location in the computer's memory system other than its actual location. Each ROM location contains one instruction or word of data and a plurality of non-data bits which may specify one of the plurality of base registers. As a word is read out of the ROM, a decoding circuit decodes the non-data bits to determine which, if any, of the base registers is specified. If a base register is specified, the decoding circuit triggers a gating circuit connected to the specified base register. The triggered gating circuit gates the contents of the specified base register into an adder, the other input to the adder coming from the data bits read from the ROM. The resulting data word, modified by the addition of the specified base register's contents, is fed into a driver circuit which transmits it to the computer. If no base register is specified by the non-data bits, the decoder circuit does not trigger any of the gating circuits, and a pattern of all zeros is provided as one input to the adder, the second input being the data bits read from the ROM. In such case, the resulting data word sent to the computer represents the unmodified data bits read out of the ROM.

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West Chester, PA, United States of America

Daniel P Drogichen