Hrl Laboratories, LLC

Other

Daniel P Docter

Miroslav Micovic

Kursad Kiziloglu

Chanh Nguyen

Mehran Matloubian

Kenneth Robert Elliott

Disclosed is a method of reducing the conductivity/charge of a layer of group III-V semiconductor doped with Sn. The method includes the steps of: forming an region of SiOon the semiconductor layer; annealing at least the semiconductor layer and the region of SiOat a temperature sufficiently high to cause atoms of the Sn dopant to leach from the semiconductor layer into the region of SiO; and removing the region of SiOafter the annealing step is performed. The method can be used, for example, during the manufacture of HEMT, PHEMT, MESFET and HBT devices.

Method of reducing the conductivity of a semiconductor and devices made thereby

A method of reducing the specific contact resistivity of a metal to semiconductor interface between a metal contact and an InP semiconductor compound. The method includes the step of increasing the amount of the group V element (P) in the semiconductor compound so that the semiconductor compound is non-stoichiometric having an excess concentration of the group V element in an amount of at least 0.1% above stoichiometric levels.

Fabrication of low resistance, non-alloyed, ohmic contacts to InP using non-stoichiometric InP layers

Bipolar junction transistor (BJT) devices, particularly heterojunction bipolar transistor (HBT) devices, and methods of making same are described. A combination of InPSb and &rgr;-type InAs is used to create extremely high speed bipolar devices which, due to reduced turn-on voltages, lend themselves to circuits having drastically reduced power dissipation. The described HBTs are fabricated on InAs or GaSb substrates, and include an InPSb emitter. The base includes In and As, in the form of InAs when on an InAs substrate, and as InAsSb when on a GaSb substrate. The collector may be the same as the base to form a single heterojunction bipolar transistor (SHBT) or may be the same as the emitter to form a double heterojunction bipolar transistor (DHBT). Heterojunctions preferably include a grading layer, which may be implemented by continuously changing the bulk material composition, or by forming a chirped superlattice of alternating materials. The grading layer preferably has delta doping planes near its ends to form an electrostatic gradient offsetting the quasi-electric field variation due to the changes in material composition, whereby effective conduction band offset may be substantially eliminated to facilitate speed, and valence band offset increased proportionally to enhance gain.

InPSb/InAs BJT device and method of making

A Double Heterojunction Bipolar Transistor (DHBT) is disclosed employing a collector of InP, an emitter of InP or other material such as InAlAs, and a base of either a selected In Ga As Sb compound, which preferably is lattice-matched to InP or may be somewhat compressively strained thereto, or of a superlattice which mimics the selected InGaAsSb compound. When an emitter having a conduction band non-aligned with that of the base is used, such as InAlAs, the base-emitter junction is preferably graded using either continuous or stepped changes in bulk material, or using a chirped superlattice. Doping of the junction may include one or more delta doping layer to improve the shift of conduction band discontinuities provided by a grading layer, or to permit a wider depletion region.

InP collector InGaAsSb base DHBT device and method of forming same

Fabrication of low resistance, non-alloyed, OHMIC contacts to INP using non-stoichiometric INP layers

Bipolar junction transistor (BJT) devices, particularly heterojunction bipolar transistor (HBT) devices, and methods of making same are described. A combination of InPSb and p-type InAs is used to create extremely high speed bipolar devices which, due to reduced turn-on voltages, lend themselves to circuits having drastically reduced power dissipation. The described HBTs are fabricated on InAs or GaSb substrates, and include an InPSb emitter. The base includes In and As, in the form of InAs when on an InAs substrate, and as InAsSb when on a GaSb substrate. The collector may be the same as the base to form a single heterojunction bipolar transistor (SHBT) or may be the same as the emitter to form a double heterojunction bipolar transistor (DHBT). Heterojunctions preferably include a grading layer, which may be implemented by continuously changing the bulk material composition, or by forming a chirped superlattice of alternating materials. The grading layer preferably has delta doping planes near its ends to form an electrostatic gradient offsetting the quasi-electric field variation due to the changes in material composition, whereby effective conduction band offset may be substantially eliminated to facilitate speed, and valence band offset increased proportionally to enhance gain.

Disclosed is a method of reducing the conductivity/charge of a layer of group III-V semiconductor doped with Sn. The method includes the steps of: forming an region of SiO on the semiconductor layer; annealing at least the semiconductor layer and the region of SiO at a temperature sufficiently high to cause atoms of the Sn dopant to leach from the semiconductor layer into the region of SiO ; and removing the region of SiO after the annealing step is performed. The method can be used, for example, during the manufacture of HEMT, PHEMT, MESFET and HBT devices.

A method of making material layers for semiconductor devices by metal organic vapor phase epitaxy includes the steps of wafer preparation, oxide desorption, growth and post growth with an accompanying reduction of a residual sheet charge at the substrate-epitaxy interface. During the oxide desorption step, a substrate is heated to a temperature minimlly necessary to remove oxide from the substrate. In accordance with such method, material layers for a low noise high electron mobility transistor (HEMT) can be grown without a bulk, buffer layer immediately adjacent the substrate. Rather, a super lattice structure is immediately adjacent to and between the substrate and a channel layer.

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Santa Monica, CA, United States of America

Daniel P Docter