Hewlett-packard Development Company, L.P.

Intel Corporation

Daniel Ortega

Paolo Faraboschi

Grigorios Magklis

Pedro Marcuello

Kyriakos A Stavrou

Demos Pavlou

Fernando Latorre

Pedro Lopez

Marc Lupon

Polychronis Xekalakis

Ayose J Falcon

Josep M Codina

Raul Martinez

Carlos Madriles

Enric Gibert Codina

Georgios Tournavitis

Mirem Hyuseinova

Crispin Gomez Requena

Christos E Kotselidis

Antonio Gonzalez

Sherif Yacoub

Jose Abad Peiro

Alejandro Martinez Vicente

Javier Carretero Casado

Juan Fernandez

Alejandro Vicente Martinez

Carlos Madriles Gimeno

Ayose Falcon Samper

Antonio Gonzelez

Marti Torrents Lapuerta

A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.

Instruction and logic for optimization level aware branch prediction

A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.

Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region

Disclosed is an apparatus and method to manage instruction cache prefetching from an instruction cache. A processor may comprise: a prefetch engine; a branch prediction engine to predict the outcome of a branch; and dynamic optimizer. The dynamic optimizer may be used to control: identifying common instruction cache misses and inserting a prefetch instruction from the prefetch engine to the instruction cache.

Managed instruction cache prefetching

An image signal processor is described. The image signal processor includes a block checking circuit. The block checking circuit comprises comparison circuitry to compare a block of luminous pixel values against respective blocks of luminous pixel values that are processed by the image signal processor after the block of luminous pixel values. The block checking circuitry further comprises circuitry to record an entry in a table if one of the blocks of respective luminous pixel values match the block of luminous pixel values. The image signal processor is to store an image signal processing resultant of the block of luminous pixel values and present the stored resultant as a respective resultant for the one of the blocks of respective luminous pixel values if the one of the blocks of respective luminous pixel values matches the block of pixel values.

Image signal processor with a block checking circuit

Example methods for finding a text reading order in a document are described in which text zones are determined, the text zones are clustered using semantic measure and correlation and a reading order is found within each of the clusters.

Method for finding text reading order in a document

An automated document processing system is configured to normalize zones obtained from a document, and to extract articles from the normalized zones. In one configuration, the system receives at least one zone from the document, and applies at least one zone-breaking factor, thereby creating normalized sub-zones within which text lines are consistent with the at least one zone-breaking factor. The normalized sub-zones may be evaluated to obtain a reading order. Adjacent sub-zones are joined if text similarity exceeds a threshold value. Weakly joined sub-zones are separated where indicated by a topic vectors analysis of the weakly joined sub-zones.

Automated document processing system

Upon an intermediary device on a network being turned on, controlling system software at the intermediary device is booted such that no public network address is ever assigned to the intermediary device. The intermediary device sends a boot message over the network to central authority software running on one or more first computing devices on the network. The central authority software in response sends messages over the network to the intermediary device and to a second computing device on the network to establish a private tunnel with one another. The intermediary device and the second computing device establish the private tunnel with one another over the network. The intermediary device then opens a remote connection to the second computing device through the private tunnel so that peripherals connected to the intermediary device as if they were directly connected to the second computing device.

Remote connection between intermediary device and computing device via central authority software

Nodes interconnected by a network have their substantially parallel execution simulated. Substantially parallel execution of the nodes during a current quantum of simulation time having a quantum length is simulated. Simulation of execution can result in simulation of inter-node data packets being transmitted over the network. When the current quantum of simulation time has elapsed, simulation of execution of the nodes is synchronized. If no inter-node data packets were transmitted in simulation during the current quantum of simulation time, then the quantum length is increased. If one or more inter-node data packets were transmitted in simulation during the current quantum of simulation time, then the quantum length is decreased. This process is then repeated for a next quantum of simulation time having the quantum length as has been increased or decreased.

Modifying length of synchronization quanta of simulation time in which execution of nodes is simulated

A method for simulating a system normally performs functional simulation of the system without performing timing simulation of the system. The method dynamically samples the functional simulation of the system at intervals to determine whether the functional simulation has entered into a new phase. Where the functional simulation has entered into a new phase, the method performs both the functional simulation and the timing simulation of the system for one or more intervals.

Dynamic sampling of functional simulation to determine whether to perform both functional and timing simulation

Instructions to be executed on a system are simulated. Representative simulation phases of the instructions, which most affect simulation results of the instructions to be executed on the system, are dynamically determined. For each representative simulation phase of the instructions, a model is selected from a number of models that provides specified accuracy with a minimal amount of simulation time, and the representative simulation phase is simulated using the model selected. The simulation results for the instructions to be executed on the system are then output.

Simulation of system execution of instructions

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Daniel Ortega