Oracle America, Inc.

Oracle International Corporation

Sun Microsystems, Inc.

Amazon Technologies, Inc.

Quanta Computer Incorporated

Daniel Nussbaum

Mark S Moir

Nir N Shavit

David Dice

Victor M Luchangco

Yosef Lev

Martin Karlsson

Guy L Steele

Ori Shalev

Alexandra Fedorova

Christopher Small

Robert Cypher

Wayne William Duso

Matteo Frigo

Peter Croft Jones

Jacob A Strauss

Michael Robert Frasca

Neal John Charbonneau

James R Goodman

Jacob David Luszcz

Xiaobin Wu

John McClain

Mark Allen Fogleman

Edward William Naim

A low latency metadata subsystem for file systems in low latency (LL) mode in a distributed file storage service (DFSS). An LL server (LLS) may receive metadata requests from an access node of the DFSS. For read operations, the LLS may check a local cache of metadata and, for cache hits, retrieve the metadata from the cache. For cache misses, the metadata may be fetched from the storage subsystem of the DFSS and cached. For write operations, the LLS may write entries into a journal for the file system and notify the access node after the journal entries are committed to the journal; the journal entries are asynchronously committed in the storage subsystem. The access node may communicate with the storage subsystem to perform data reads and writes for the LL file system.

Low latency distributed storage service

An example method to perform rate control in a parallel encoding system including a plurality of parallel encoders is disclosed. The method may comprise determining a quantization parameter for one of the plurality of parallel encoders based on a measure of parallelism of the plurality of parallel encoders. The method may further comprise providing the quantization parameter to the one of the plurality of parallel encoders to encode a chunk of a video sequence to generate an encoded chunk based on the quantization parameter.

Rate control method and system

Systems and methods described herein for performing incremental register checkpointing may employ a special register to indicate which registers have already been checkpointed. This register may include one bit per register. These systems may also include a special pointer register whose value identifies a location in user memory or in dedicated on-chip storage at which a copy of a register's value should be saved by a checkpointing operation. Only registers modified during speculative execution or execution of a transaction may be checkpointed (e.g., when register modifying instructions are encountered) and subsequently restored (e.g., due to misspeculation or transaction abort), rather than all of the registers of the processor. Each register may be checkpointed at most once for a given speculative episode or atomic transaction. Setting a bit in the special register may prevent checkpointing of the corresponding register. Setting all of the bits in the special register may disable checkpointing.

System and method for performing incremental register checkpointing in transactional memory

A thread scheduling technique for assigning multiple threads on a single integrated circuit is dependent on the CPIs of the threads. The technique attempts to balance, to the extent possible, the loads among the processing cores by assigning threads of relatively long-latency (low CPIs) with threads of relatively short-latency (high CPIs) to the same processing core.

Thread scheduling in chip multithreading processors

A computer system includes an integrated circuit that has a plurality of processing cores fabricated therein and configured to perform operations in parallel. Each processing core is configured to process multiple threads, where a thread is assigned to one of the plurality of processing cores dependent on a cache hit rate of the thread.

The transactional memory system described herein may implement parallel co-transactions that access a shared memory such that at most one of the co-transactions in a set will succeed and all others will fail (e.g., be aborted). Co-transactions may improve the performance of programs that use transactional memory by attempting to perform the same high-level operation using multiple algorithmic approaches, transactional memory implementations and/or speculation options in parallel, and allowing only the first to complete to commit its results. If none of the co-transactions succeeds, one or more may be retried, possibly using a different approach and/or transactional memory implementation. The at-most-one property may be managed through the use of a shared 'done' flag. Conflicts between co-transactions in a set and accesses made by transactions or activities outside the set may be managed using lazy write ownership acquisition and/or a priority-based approach. Each co-transaction may execute on a different processor resource.

System and method for executing a transaction using parallel co-transactions

The system and methods described herein may exploit hardware transactional memory to improve the performance of a software or hybrid transactional memory implementation, even when an entire user transaction cannot be executed within a hardware transaction. The user code of an atomic transaction may be executed within a software transaction, which may collect read and write sets and/or other information about the atomic transaction. A single hardware transaction may be used to commit the atomic transaction by validating the transaction's read set and applying the effects of the user code to memory, reducing the overhead associated with commitment of software transactions. Because the hardware transaction code is carefully controlled, it may be less likely to fail to commit. Various remedial actions may be taken before retrying hardware transactions following some failures. If a transaction exceeds the constraints of the hardware, it may be committed by the software transactional memory alone.

System and method for committing results of a software transaction using a hardware transaction

One embodiment provides a system that facilitates the execution of a transaction for a program in a hardware-supported transactional memory system. During operation, the system records a failure state of the transaction during execution of the transaction using hardware transactional memory mechanisms. Next, the system detects a transaction failure associated with the transaction. Finally, the system provides an advice state associated with the recorded failure state to the program to facilitate a response to the transaction failure by the program.

Advice-based feedback for transactional execution

The software transactional memory system described herein may implement a revocable mechanism for managing read ownership in a shared memory. In this system, write ownership may be revoked by readers or writers at any time other than when a writer transaction is in a commit state, wherein its write ownership is irrevocable. An ownership record associated with one or more locations in the shared memory may include an indication of whether the memory locations are owned for writing, and an identifier of the latest writer. A read ownership array may record data indicating which, if any, threads currently own the memory locations for reading. The system may provide an efficient read-validation operation, in which a full read-set validation is avoided unless a change in a global read-write conflict counter value indicates a potential conflict. The system may support a wide range of contention management policies, and may provide implicit privatization.

System and method for performing visible and semi-visible read operations in a software transactional memory

One embodiment provides a system that facilitates the execution of a transaction for a program in a hardware-supported transactional memory system. During operation, the system records a misspeculation indicator of the transaction during execution of the transaction using hardware transactional memory mechanisms. Next, the system detects a transaction failure associated with the transaction. Finally, the system provides the recorded misspeculation indicator to the program to facilitate a response to the transaction failure by the program.

Facilitating transactional execution through feedback about misspeculation

Systems and methods may reduce overhead associated with read set consistency validation in software transactional memory implementations. These systems and methods may employ an inconsistency-aware compiler-library technique, in which an inconsistency-aware compiler communicates to various inconsistency-aware library functions knowledge about whether a given transaction has read consistent values to date. The inconsistency-aware library functions may exploit this information to avoid the need to validate the transaction, or portions thereof. If read set values are known to be consistent prior to the function call, the compiler may pass a parameter value to the function indicating as much. Otherwise, it may pass a value indicating that the read set values may be inconsistent. An inconsistency-aware function may determine that it will not perform a dangerous action, even though its parameters may not be consistent. Otherwise, the inconsistency-aware function may invoke a validation operation, or may perform other error avoidance operations.

Systems and methods for supporting software transactional memory using inconsistency-aware compilers and libraries

A phased transactional memory (PhTM) may support a plurality of transactional memory implementations, including software, hardware, and hybrid implementations, and may provide mechanisms for dynamically transitioning between transactional memory modes in response to changing workload characteristics; upon discovering that the current mode does not perform well, is not suitable, or does not support functionality required for particular transactions; or according to scheduled phases. A system providing PhTM may be configured to transition from a first transactional memory mode to a second transactional memory mode while ensuring that transactions executing in the first transactional memory mode do not interfere with correct execution of transactions in the second transactional memory mode. The system may be configured to abort transactions in progress or to wait for transactions to complete, be aborted, or reach a safe transition point before transitioning to a new mode, and may use a global mode indicator in coordinating transitions.

System and method for supporting phased transactional memory modes

In general, in one aspect, the invention relates to a method of establishing a queue-based lock including inserting a first qnode into a local queue, where the first qnode is associated with a first thread, splicing the local queue into the global queue, obtaining a lock for the first thread when the first qnode is at the head of the global queue, and executing a critical section of the first thread after obtaining the lock.

Hierarchical queue-based locks

Producers and consumer processes may synchronize and transfer data using a shared data structure. After locating a potential transfer location that indicates an EMPTY status, a producer may store data to be transferred in the transfer location. A producer may use a compare-and-swap (CAS) operation to store the transfer data to the transfer location. A consumer may subsequently read the transfer data from the transfer location and store, such as by using a CAS operation, a DONE status indicator in the transfer location. The producer may notice the DONE indication and may then set the status location back to EMPTY to indicate that the location is available for future transfers, by the same or a different producer. The producer may also monitor the transfer location and time out if no consumer has picked up the transfer data.

Scalable method for producer and consumer elimination

A system for controlling contention between conflicting transactions in a transactional memory system. During operation, the system receives a request to access a cache line and then determines if the cache line is already in use by an existing transaction in a cache state that is incompatible with the request. If so, the system determines if the request is from a processor which is in a polite mode. If this is true, the system denies the request to access the cache line and continues executing the existing transaction.

Growing community of inventors

Cambridge, MA, United States of America

Daniel Nussbaum