International Business Machines Corporation

Daniel Nelson Maynard

Mark Alan Lavin

Jason D Hibbeler

William C Leipold

David L DeMaris

Evanthia Papadopoulou

Robert J Allen

Maharaj Mukherjee

Bette L Bergman Reuter

Jeffrey P Gambino

Mark David Jaffe

Eric Jeffrey White

John Anthony Bracchitta

Michael E Scaman

Robert F Walker

Richard L Rassel

Timothy G Dunham

Kevin N Ogg

Edward W Sengle

Mervyn Y Tan

Shi Zhong

John J Ellis-Monaghan

Albert Manhee Chu

Gustavo Enrique Tellez

Richard John Rassel

Juergen Koehl

Michael S Gray

Daria Rose Dooling

Ralph James Williams

Faye D Baker

Raymond J Rosner

David C Reynolds

Mitchell R DeHond

Brian Douglas Pfeifer

Reginald B Wilcox, Jr

Sarah C Braasch

Sarah C Prue

Sani Richard Nassif

Dennis Merton Newns

Jeanne P Bickford

Rouwaida N Kanj

Markus Buehler

Kevin W McCullen

Douglas Wayne Kemerer

Matthew Thomas Guzowski

William John Livingstone

Wilm Ernst Donath

Young O Kim

Archibald John Allen

Jeanne Paulette Spence Bickford

Lijiang L Wang

Jeffery Peter Gambino

Donald G Chesebro

Alan Dziedzic

Sharon B Sisler

Jeffrey P Bonn

Richard Charles Whiteside

Betty L Bergman Reuter

Peter S Wissell

CMOS pixel sensors with multiple pixel sizes and methods of manufacturing the CMOS pixel sensors with implant dose control are provided. The method includes forming a plurality of pixel sensors in a same substrate and forming a masking pattern over at least one of the plurality of pixel sensors that has a pixel size larger than a non-masked pixel sensor of the plurality of pixel sensors. The method further includes providing a single dosage implant to the plurality of pixel sensors. The at least one of the plurality of pixel sensors with the masking pattern receives a lower dosage than the non-masked pixel sensor.

Pixel sensors of multiple pixel size and methods of implant dose control

A pixel structure for an image sensor includes a semiconductor material portion having a coplanar and contiguous semiconductor surface and including four photodiodes, four channel regions, and a common floating diffusion region. Each of the four channel regions is directly adjoined to one of the four photodiodes and the common floating diffusion region. The four photodiodes are located within four different quadrants as defined employing a vertical line passing through a point within the common floating diffusion region as a center axis. The common floating diffusion region, a reset gate transistor, a source follower transistor, and a row select transistor are located within four different quadrants as defined employing a vertical line passing through a point within one of the photodiodes as an axis.

Image sensor pixel structure employing a shared floating diffusion

A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.

System and method for testing pattern sensitive algorithms for semiconductor design

A method, apparatus, system, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.

Apparatus and computer program product for semiconductor yield estimation

A complementary metal-oxide-semiconductor (CMOS) image sensor comprises a first photosensitive diode comprising a first semiconductor material is formed in a first semiconductor substrate. A second photosensitive diode comprising a second semiconductor material, which has a different light detection wavelength range than the first semiconductor material, is formed in a second semiconductor substrate. Semiconductor devices for holding and detecting charges comprising a sensing circuit of the CMOS image sensor may also be formed in the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first photosensitive diode is located underneath the second photosensitive diode. The vertical stack of the first and second photosensitive diodes detects light in the combined detection wavelength range of the first and second semiconductor materials. Sensing devices may be shared between the first and second photosensitive diodes.

Optical sensor including stacked photodiodes

Optical sensor including stacked photosensitive diodes

Optimizing an integrated circuit design to improve manufacturing yield using manufacturing data and algorithms to identify areas with high probability of failures, i.e. critical areas. The process further changes the layout of the circuit design to reduce critical area thereby reducing the probability of a fault occurring during manufacturing. Methods of identifying critical area include common run, geometry mapping, and Voronoi diagrams. Optimization includes but is not limited to incremental movement and adjustment of shape dimensions until optimization objectives are achieved and critical area is reduced.

IC layout optimization to improve yield

Disclosed herein are embodiments of a system and an associated method for analyzing an integrated circuit to determine the value of a particular attribute (i.e., a physical or electrical property) in that integrated circuit. In the embodiments, an open deterministic sequencing technique is used to select a sequence of points representing centers of sample windows in an integrated circuit layout. Then, the value of the particular attribute is determined for each sample window and the results are accumulated in order to infer an overall value for that particular attribute for the entire integrated circuit layout. This sequencing technique has the advantage of allowing additional sample windows to be added and/or the sizes and shapes of the windows to be varied without hindering the quality of the sample.

Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing technique

A method, apparatus, and computer program product for visually indicating the interaction between one or more edges of a design that contribute to a defined critical area pattern.

Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design

A method, system and program product to model an IC design to include dimensions such as a local width and spacing of IC shapes in a consistent fashion. In particular, the invention uses a core portion of Voronoi diagrams to partition edges of a shape into intervals and assigns at least one dimension to each interval such as a local width and spacing. Dimension assignment can be made as any desirable definition set for width and spacing, e.g., numerical values or continuous dimension-dependent design rules. Design rule checking for dimension-dependent spacing rules given in any arbitrary functional form of width and spacing is possible. Application of the invention can be made anywhere the width and spacing of VLSI shapes play a role, e.g., relative to a single edge, neighboring edges, neighboring shapes, and/or for edges in more than one layer of the IC design.

IC design modeling allowing dimension-dependent rule checking

A computer program product for generating test patterns for a pattern sensitive algorithm. The program product includes code for extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.

Testing pattern sensitive algorithms for semiconductor design

An integrated circuit system and program product for predicting yield of a VLSI design. An integrated circuit system is provided including a system for identifying and grouping sub-circuits contained within an integrated circuit design by circuit type; a critical area calculation system for determining critical area values for different regions, wherein each different region is associated with a circuit type; a tallying system for calculating a plurality of tallies of critical area values based on circuit type; and a plurality of modeling subsystems for separately modeling each of the plurality of tallies based on circuit type.

Content based yield prediction of VLSI designs

A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.

Physical design characterization system

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Craftsbury Common, VT, United States of America

Daniel Nelson Maynard