Bae Systems Information and Electronic Systems Integration Inc.

Retro Reflective Optics, LLC

Schilmass Co. L.l.c.

Lateral Research Limited Liability Company

Daniel N Carothers

Craig M Hill

Vu Anh Vu

Andrew T S Pomerene

Rick L Thompson

Timothy J Conway

Andrew T Pomerene

Robert L Kamocsai

Joe Giunta

Jonathan N Ishii

Richard Berger

Jefferson E Odhner

A method for growing germanium epitaxial films is disclosed. Initially, a silicon substrate is preconditioned with hydrogen gas. The temperature of the preconditioned silicon substrate is then decreased, and germane gas is flowed over the preconditioned silicon substrate to form an intrinsic germanium seed layer. Next, a mixture of germane and phosphine gases can be flowed over the intrinsic germanium seed layer to produce an n-doped germanium seed layer. Otherwise, a mixture of diborane and germane gases can be flowed over the intrinsic germanium seed layer to produce a p-doped germanium seed layer. At this point, a bulk germanium layer can be grown on top of the doped germanium seed layer.

Method for growing germanium epitaxial films

A system is provided for the manufacture of carbon based electrical components including, an ultraviolet light source; a substrate receiving unit whereby a substrate bearing a first layer of carbon based semiconductor is received and disposed beneath the ultraviolet light source; a mask disposed between the ultraviolet light source and the carbon based semiconductor layer; a doping agent precursor source; and environmental chemical controls, configured such that light from the ultraviolet light source irradiates a doping agent precursor and the first carbon layer.

Photo-patterned carbon electronics

A device for medium wavelength infrared emission and a method for the manufacture thereof is provided. The device has a semiconductor substrate; a passive hermetic barrier disposed upon the substrate, and an emitter element disposed within said hermetic barrier; and a mirror.

Process to fabricate integrated MWIR emitter

An improved method for manufacturing a lateral germanium detector is disclosed. A detector window is opened through an oxide layer to expose a doped single crystalline silicon layer situated on a substrate. Next, a single crystal germanium layer is grown within the detector window, and an amorphous germanium layer is grown on the oxide layer. The amorphous germanium layer is then polished to leave only a small portion around the single crystal germanium layer. A dielectric layer is deposited on the amorphous germanium layer and the single crystal germanium layer. Using resist masks and ion implants, multiple doped regions are formed on the single crystal germanium layer. After opening several oxide windows on the dielectric layer, a refractory metal layer is deposited on the doped regions to form multiple germanide layers.

Method for manufacturing lateral germanium detectors

A method is provided for the integration of an optical gain material into a Complementary metal oxide semiconductor device, the method comprising the steps of: configuring a workpiece from a silicon wafer upon which is disposed an InP wafer bearing an epitaxy layer; mechanically removing the InP substrate; etching the InP remaining on epitaxy layer with hydrochloric acid; depositing at least one Oxide pad on revealed the epitaxy layer; using the Oxide pad as a mask during a first pattern etch removing the epitaxy to an N level; etching with a patterned inductively coupled plasma (ICP) technique; isolating the device on the substrate with additional pattern etching patterning contacts, applying the contacts.

Integration CMOS compatible of micro/nano optical gain materials

Techniques are disclosed for efficiently fabricating semiconductors including waveguide structures. In particular, a two-step hardmask technology is provided that enables a stable etch base within semiconductor processing environments, such as the CMOS fabrication environment. The process is two-step in that there is deposition of a two-layer hardmask, followed by a first photolithographic pattern, followed by a first silicon etch, then a second photolithographic pattern, and then a second silicon etch. The process can be used, for example, to form a waveguide structure having both ridge and channel configurations, or a waveguide (ridge and/or channel) and a salicide heater structure, all achieved using the same hardmask. The second photolithographic pattern allows for the formation of the lower electrical contacts to the waveguides (or other structures) without a complicated rework of the hardmask.

Two-step hardmask fabrication methodology for silicon waveguides

A method for the manufacture of carbon based electrical components is herein presented. In the method a wafer substrate is provided upon which a first layer of carbon based semiconductor is deposited. The first layer of carbon based semiconductor is introduced to a first doping agent precursor and the first doping agent precursor and first layer of carbon based semiconductor are irradiated with light having a wavelength in the ultraviolet spectrum thereby selectively doping areas of the first layer of carbon based semiconductor.

Method for the production of photo-patterned carbon electronics

A waveguide optical gyroscope is disclosed. The waveguide optical gyroscope includes a laser, two detectors, a set of couplers and a set of waveguides. The laser generates a light beam. A first waveguide guides the light beam to travel in a first direction, and a second waveguide guides the light beam to travel in a second direction. The first and second waveguides are coupled to several ring waveguides via the couplers. The first detector detects the arrival of the light beam traveling from the first waveguide, and the second detector detects the arrival of the light beam traveling from the second waveguide.

High-index contrast waveguide optical gyroscope having segmented paths

An apparatus and method is provided for the testing of an optical bus, that method having: loading transmission test data and address information for at least one receiving cell via an electronic bus in a first register; setting a clock rate for the optical bus; employing the optical bus to transmit the test data from the first register to the at least one receiving cell; reading out received test data from the receiving cell via the electronic bus; correlating the received test data from the first register with the transmission test data; analyzing errors in the received data and handling of the received data by the bus.

Components and configurations for test and valuation of integrated optical busses

Techniques are disclosed that facilitate fabrication of semiconductors including structures and devices of varying thickness. One embodiment provides a method for semiconductor device fabrication that includes thinning a region of a semiconductor wafer upon which the device is to be formed thereby defining a thin region and a thick region of the wafer. The method continues with forming on the thick region one or more photonic devices and/or partially depleted electronic devices, and forming on the thin region one or more fully depleted electronic devices. Another embodiment provides a semiconductor device that includes a semiconductor wafer defining a thin region and a thick region. The device further includes one or more photonic devices and/or partially depleted electronic devices formed on the thick region, and one or more fully depleted electronic devices formed on the thin region. An isolation area can be formed between the thin region and the thick region.

Multi-thickness semiconductor with fully depleted devices and photonic integration

One embodiment of the present invention provides a system for the transmission of data between an optical bus and an electronic component at a speed independent from a clock speed of the electrical component; the system comprising an optical data storage component communicating with both the optical bus and the electrical component; the optical data storage component being configured to hold data transmitted on the optical bus until said electrical component is available.

Bi-rate adaptive optical transfer engine

Techniques are disclosed for optical switching and data control, without the interaction of electronic switching speeds. In one example embodiment, a common cavity optical latch is provided that that can hold an optical state for an extended period of time, and the operation of which is controlled optically. Optical phase control allows optical modal switching to be employed between two common optical cavities, using incident optical signals and the way in which the cavities manipulate the phase within them to lock in one or the other configuration, thereby forming an optical latch. The optical latch is implemented in an integrated fashion, such as in a CMOS environment.

Integrated optical latch

A method for fabricating photonic and electronic devices on a substrate is disclosed. Multiple slabs are initially patterned and etched on a layer of a substrate. An electronic device is fabricated on a first one of the slabs and a photonic device is fabricated on a second one of the slabs, such that the electronic device and the photonic device are formed on the same layer of the substrate.

Method for fabricating electronic and photonic devices on a semiconductor substrate

A method for the singulation of integrated circuit die, the method including: etching a semiconductor layer disposed on a silicon oxide dielectric layer, thereby forming a trench defining a boundary of the die; depositing a silicon nitride layer in the trench; coating the semiconductor layer with an oxide layer such that the trench is filled; removing part of the oxide layer from the semiconductor layer such that the oxide layer only remains in the trench; mounting the semiconductor layer to a carrier; removing the silicon oxide dialectic layer, the nitride layer, and the oxide layer; and releasing the die from the carrier. The method is suitable for irregularly shaped or extremely small die and is compatible with traditional CMOS processes.

Growing community of inventors

Oro Valley, AZ, United States of America

Daniel N Carothers