Itt Industries, Inc.

Daniel Mlynek

Friedrich Schmidtpott

Laurin C Freyberger

Peter M Flamm

Wolfgang Gollinger

Dieter Holzmann

Albrecht Gerlach

Dirk Hoffmeister

Alfred Praxmarer

The adder/subtracter disclosed sums a plurality of n-digit binary-coded numbers (A, B, C . . . Z) successively by forming corresponding partial sums (Sb, Sc . . . Sz) according to the following recursive formula:

Binary MOS ripple-carry parallel adder/subtracter and adder/subtracter

In this IC set, the dark currents and the white levels of the three electron guns, the leakage currents of the cathodes, and a light-detector current are measured during four successive vertical blanking intervals. The cathode leakage currents and the dark currents are measured in the first half of the vertical blanking interval, and the light-detector current and the white-level currents are measured at the end of this interval. From these measured data and alignment data stored in a reprogrammable memory (ps), a microprocessor (mp) contained together with the memory (ps) in an integrated circuit (ic2) derives operating data for the picture tube (b) as well as further data. These operating data are transferred over a wire of a chroma bus (cb), over which chroma signals are transferred during the vertical sweep, into a shift register (sr) of a further integrated circuit (ic3) at the beginning of each vertical blanking interval, from where they are passed on to the picture tube (b) in groups via digital-to-analog converters and analog amplifiers. By the use of the chroma bus for a dual purpose, and the successive measurements of the above-mentioned picture-tube data, a saving of external terminals of the integrated circuits (ic1, ic2, ic3) is achieved.

Set of three integrated circuits for digital video signal processing in

An improved digital integrated chrominance-channel circuit having gain control for color-television receivers includes at least one integrated circuit for digitally processing the composite color signal. The circuit includes a first limiter inserted between a parallel multiplier and a burst-amplitude-measuring stage, and a control stage including a parallel subtracter whose minuend input is fed with a reference signal, and whose subtrahend input is connected to the output of the burst-amplitude-measuring stage. A digital accumulator whose enable input is presented with a signal derived from the trailing edge of a burst gating signal is used as an integrator.

Digital integrated chrominance-channel circuit with gain control

In this IC set, the dark currents and the white levels of the three electron guns, the leakage currents of the cathodes, and a light-detector current are measured during four successive vertical blanking intervals. The cathode leakage currents and the dark currents are measured in the first half of the vertical blanking interval, and the light-detector current and the white level currents are measured at the end of this interval. From these measured data and alignment data stored in a reprogrammable memory (ps), a microprocessor (mp) contained together with the memory (ps) in an integrated circuit (ic2) derives operating data for the picture tube (b) as well as further data. These operating data are transferred over a wire of a chroma bus (cb), over which chroma signals are transferred during the vertical sweep, into a shift register (sr) of a further integrated circuit (ic3) at the beginning of each vertical blanking interval, from where they are passed on to the picture tube (b) in groups via digital-to-analog converters and analog amplifiers. By the use of the chroma bus for a dual purpose, and the successive measurements of the above-mentioned picture-tube data, a saving of external terminals of the integrated circuits (ic1, ic2, ic3) is achieved.

A fast MOS driver circuit for digital signals having a small current consumption and a good signal-to-noise ratio comprises an output inverter, a pre-inverter and of an enhancement-type transistor having its source-drain path connected in parallel to that of the load transistor of the output inverter (IA). The gate of the enhancement-type transistor and the gates of the load transistors of the output and pre-inverters are coupled to the output of the pre-inverter. The W/L-ratio of the enhancement-type transistor is almost the same as that of the switching transistor of the output inverter. The gates of the switching transistors are connected to one another. The load transistors are of the depletion type while the switching transistors are of the enhancement type. An embodiment is disclosed employing the above circuit and an additional pre-inverter circuit arrangement operating on a two-phase ratio technique controlled by a two-phase clock signal to match capacitances greater than that matched by the above circuit.

Fast MOS driver stage for digital signals

Unlike prior art parallel adders, which employ conventional EXCLUSIVE-OR gates, the parallel adder disclosed uses special EXCLUSIVE-NOR gates constructed from only three transistors, so that a considerable space-saving and a reduction of power dissipation are achieved on the integrated-circuit chip. Instead of noninverted digit signals, inverted digit signals are used to form the E and D signals which are combined by means of a complex gate for each binary weight to form the inverted carry signal of this weight. This complex gate includes a number of AND elements equal to the number of the stage, and a NOR element combining the outputs of these AND elements and the D signal of this stage. The inverted carry signal of a stage and the inverted subtotal signal of the next higher-order stage are combined by means of an EXCLUSIVE-NOR gate of the above-mentioned special circuit construction to form the noninverted sum signal of the next higher order stage. The inverted subtotal signal of each stage is also provided by an EXCLUSIVE-NOR gate of the above-mentioned special circuit construction combining the E and D signals of that stage.

Binary MOS carry-look-ahead parallel adder

The invention discloses a method and apparatus for digitally generating a variable pulse train with some pulses in a period T, the number of which can be changed step by step. The pulse train can be used for generating a variable dc voltage particularly for the tuning voltage of TV receiver capacitance diodes.

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Wolfgantzen, France

Daniel Mlynek