Atmel Corporation

Daniel Meyer

Daniel Scott Cohen

John L Fagan

Mikhail Itskovich

A voltage regulator is disclosed. The voltage regulator includes a comparator for providing a gated output signal; and a state machine for receiving the gated output signal. The voltage regulator further includes at least one switch cell controlled by the state machine, for delivering charge to a load. Accordingly, a voltage regulator in accordance with the present invention yields N times (where N is an integer greater than one) the linear efficiency over typical linear regulators without requiring any external components. Therefore improved regulator efficiency is provided for low power devices.

Voltage regulator for an integrated circuit

Aspects provide discrete-time analog, digitally programmable filtering. A filter includes a plurality of transistors coupled as a current mode circuit. Further included is a switch for use in switching the plurality of transistors in and out to tune the current mode circuit, wherein adjustable low bandwidth filtering using small silicon area without passive components is achieved.

Discrete-time analog, digitally programmable filter and method

A modulation method, referred to as dual phase pulse modulation (DPPM), represents digital data as a series of high and low pulses whose widths represent groups of M data bits, with both the high and low pulses representing successive M-bit groups. Each of the 2possible data values for a group of M data bits uniquely corresponds to one of 2distinct pulse widths. This modulation method is essentially clockless, with data being decoded from a signal by detecting each pulse's width with respect to the last transition. Power consumption is reduced by having M data bits represented for each pulse transition, and by using both the high and low pulses to represent data.

Method for performing dual phase pulse modulation

A dual phase pulse modulation (DPPM) decoder circuit processes a DPPM signal, which is in the form of a series of high and low pulses whose pulse widths represent successive groups of M data bits, so as to recover data carried by the signal. Each of the 2possible data values of an M-bit group corresponds to one of 2distinct pulse widths. Circuit blocks determine the width of each pulse by piping the DPPM signal through a short delay chain and using the delayed outputs to clock flip-flop registers to sample the non-delayed signal. The registered output is interpreted by logic gates to obtain the corresponding M-bit groups. The decoder circuit may have two substantially identical pulse width determining blocks, one receiving the DPPM signal for measuring high pulses, and the other receiving an inverted DPPM signal for measuring the low pulses.

Dual phase pulse modulation decoder circuit

A delay locked loop circuit with improved restart features. The circuit includes a clock input, a clock output, a divider circuit, phase detector and control logic. The circuit includes a means for implementing a binary search of outputs from the control logic for generating a calibration bit, which is applied to the transmission on an output line.

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Woodstock, MD, United States of America

Daniel Meyer