International Business Machines Corporation

Daniel Mathew Wronski

Sebastian Theodore Ventrone

Stephen William Mahin

Michael Joseph Peters

Kevin William McCullen

John J Bergkvist,Jr

A computer processor architecture which employs an on-chip cache macro and an on-chip memory map is described. The memory map contains indicia of the cachability of different segments of off-chip memory, preferably along with an indication of the read/write status of each off-chip memory segment. A processor generated address signal is then compared on-chip with the memory map to ascertain whether the generated signal falls within a segment which is cachable or uncachable and which is read-only or read/write.

On-chip memory map for processor cache macro

A method and apparatus for compressing cacheable data stored in one or more write back buffers is described herein. A cacheable data element includes an address component, a data component and a byte enable component. Generally, the method includes comparing the address component of a first cacheable data element stored in a first write back buffer with the address component of a second cacheable data element. This second cacheable data element may be an incoming data element from the processor or a data element stored in a second write back buffer. If the two address components are equal, then compression is performed. In one implementation, compression is performed by overlaying the data component of the first cacheable data element with the data component of the second cacheable data element resulting in a compressed data component. In addition, the byte enable component of the first cacheable data element and the byte enable component of the second cacheable data element are combined resulting in a combined byte enable component. The combined byte enable component indicates which bits of the compressed data component are valid.

Growing community of inventors

Essex Junction, VT, United States of America

Daniel Mathew Wronski