Ambiq Micro, Inc.

Intel Corporation

Daniel Martin Cermak

Scott McLean Hanson

Stephen James Sheafor

Eric Jonathan Deal

Donovan Scott Popps

Mark A Baur

Manoj R Sastry

Ioannis T Schoinas

Yousof Mortazavi

Ramakanth Kondagunturi

Richard Trujillo

Karempudi V Ramarao

Christophe J Chevallier

Roger David Serwy

Howard P Tsoi

Marc William Miller

Jack K Matheson

John E Derrick

Scott McLean

Udi Kalekin

Bryan Dobbs

Ying Fai Tong

Brendon D Cahoon

A low-power system-on-chip includes an originating controller, a fabric, and a power controller. The originating controller is configured to initiate a memory transaction request including a source address. The fabric includes an arbiter configured to receive the memory transaction request and determine a first memory device associated with the memory transaction request. The power controller is configured to selectively change a first memory bank of the first memory device from a first power mode to a second power mode based at least in part on the source address. The fabric is configured to perform a memory operation by (a) receiving stored data from memory storage locations corresponding to the source address when the memory transaction request includes a read request, and (b) sending data included in the memory transaction request to the memory storage locations when the memory transaction request includes a program or a write request.

On-demand activation of memory path during sleep or active modes

Embodiments of the disclosure are directed to a system having a memory module, a voltage generation module, and a plurality of multiplexors. The memory module has a plurality of memory blocks. The voltage generation module supplies two or more voltage rails. The multiplexors are electrically connected to the voltage generation module. Each memory block is electrically connected to one of the multiplexors. Each multiplexor is configured to switch between the two or more voltage rails based on an operational parameter of each memory block. The operational parameter of each memory block may be process control speed, storage status, an operating mode, temperature, or any combination thereof. The operating mode may further be an active mode, a standby mode, and a deep sleep mode.

Memory module with fine-grained voltage adjustment capabilities

A microcontroller system includes a processing unit supporting at least one near or sub Vt circuit and a plurality of memory blocks, each memory block connected to a DMA controller and independently power controlled. A power control system uses power gates to power control at least the memory blocks. In some embodiments, a wake-up interrupt controller is connected to the power control system and a voltage regulator system is used to supply voltage to separate power domains, with the voltage regulator systems controlled at least in part by power gates operated by the power control system. A plurality of clocks can be connected to define clock domains associated with separate power domains.

Very low power microcontroller system

A microcontroller system that includes a central processing unit (CPU), a first system memory, a first peripheral module, and a DMA controller is disclosed. The DMA controller includes a DMA processor, a DMA memory, and a DMA interconnect. The DMA memory stores information associated with the DMA processor. The DMA processor receives a command from the CPU or a signal from a peripheral processor of the first peripheral module that a first data transfer is requested. The DMA processor receives first data from the first system memory or the first peripheral module. The DMA processor, based at least in part on the information stored in the DMA memory, transmits the first data to the first peripheral module or the first system memory, thereby sparing the CPU from managing the transferring of the first data.

Enhanced peripheral processing system to optimize power consumption

A flash memory system for use in an electronic system comprising an integrated circuit such as a microcontroller. The flash memory system embodies one or more circuits adapted to operate at sub- or near-threshold voltage levels. These low-power circuits are selectively activated or de-activated to balance power dissipation with the response time of the memory system required in particular applications.

Sub-threshold enabled flash memory system

A method and system for enforcing access control to system resources and assets. Security attributes associated with devices that initiate transactions in the system are automatically generated and forwarded with transaction messages. The security attributes convey access privileges assigned to each initiator. One or more security enforcement mechanisms are implemented in the system to evaluate the security attributes against access policy requirements to access various system assets and resources, such as memory, registers, address ranges, etc. If the privileges identified by the security attributes indicate the access request is permitted, the transaction is allowed to proceed. The security attributes of the initiator scheme provides a modular, consistent secure access enforcement scheme across system designs.

Method for enforcing resource access control in computer systems

Method, apparatus, and system for qualifying CPU transactions with security attributes. Immutable security attributes are generated for transactions initiator by a CPU or processor core that identifying the execution mode of the CPU/core being trusted or untrusted. The transactions may be targeted to an Input/Output (I/O) device or system memory via which a protected asset may be accessed. Policy enforcement logic blocks are implemented at various points in the apparatus or system that allow or deny transactions access to protected assets based on the immutable security attributes generated for the transactions. In one aspect, a multiple-level security scheme is implemented under which a mode register is updated via a first transaction to indicate the CPU/core is operating in a trusted execution mode, and security attributes are generated for a second transaction using execution mode indicia in the mode register to verify the transaction is from a trusted initiator.

Method, apparatus, system for qualifying CPU transactions with security attributes

Systems, methods and apparatuses for embodiments of a transformation engine for structured documents are disclosed. More specifically, instruction code may be generated by a compiler from transformation instructions for a structured document. Embodiments of the transformation engine may comprise hardware circuitry operable to execute the instruction code to process a structured document according to the transformation instructions such that output for an output document is generated.

Method, system and apparatus for a transformation engine for use in the processing of structured documents

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Austin, TX, United States of America

Daniel Martin Cermak