Freescale Semiconductor,inc.

Nxp Usa, Inc.

Motorola Corporation

Hitachi, Ltd.

Edgcore Technology, Inc.

Edge Computer Corporation

Arix Computer

Daniel M McCarthy

Joseph Charles Circello

Nicholas Julian Richardson

John J Vaglica

Peter Jeremy Wilson

William B Ledbetter, Jr

Gabriel R Munguia

David J Schimke

John D Mitchell

Gregory C Edgington

Richard Duerden

Kristen A Hausman

James G Gay

Yoshihiro Miyazaki

Ruey J Yu

Hiroaki Fukumaru

Paul William Hollis

Henri Cloetens

Bridget Catherine Hooser

Renny Lee Eisele

Sylvia M Thirtle

Nancy H Woo

Ujwala R Malwade

Siochi Takaya

Cliff L Parrott

Kirsten A Hausman

Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed.

Processing systems and methods for transitioning between privilege states based on an address of a next instruction to be fetched

A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.

Data processor device supporting selectable exceptions and method thereof

A method includes generating least-recently-used location information for a shared set-associative multi-access cache and next-to least-recently-used location information for the shared set-associative multi-access cache. The method includes concurrently accessing a shared set-associative multi-access cache in response to a first memory request from a first memory requestor and a second memory request from a second memory requestor based on the least-recently-used location information and the next-to least-recently-used location information. The method may include updating the least-recently-used location information and the next-to least-recently-used location information in response to concurrent access to the shared set-associative multi-access cache according to the first memory request and the second memory request. The method may include independently handling the first and second memory accesses concurrently in response to first and second set fields being different and cooperatively handling the first and second memory access concurrently in response to first and second set fields identifying a target set.

Shared cache protocol for parallel search and replacement

A storage location of a device that can be configured to act as a master in a particular security mode, such as a Direct Memory Access (DMA) having one or more channels, can be programmed to indicate a security indicator to be provided when configured to operate as a master device.

Programmable direct memory access channels

Methods and systems for transitioning between a user state and a supervisor state based on a next instruction fetch address

Access requests to access data operands from memory space designated as a type of execute-only memory are allowed to precede in response to determining that the operand access request was generated using a particular type of addressing mode.

Method and device implementing execute-only memory protection

Data processing device and method of halting exception processing

In response to determining an event has occurred, information is stored at a trace buffer of an integrated circuit. When the trace buffer is full, execution of instructions at a CPU is halted to allow the trace buffer information to be accessed at an external interface to the integrated circuit device. The CPU is continually halted as the trace buffer is filled to facilitate retrieving all information written to the trace buffer.

Data processor device having trace capabilities and method

A system and method for performance monitoring in processors is provided. The system and method evaluates the performance of the processor by counting selected events during one or more defined periods. The performance monitor provides improved performance characterization by providing highly-configurable start-stop control over the event counting.

Performance monitor with precise start-stop control

A system ( ) implements user programmable addressing modes in response to control information contained within an input address. Encoded control information stored in a plurality of user programmed address permutation control registers ( ) is used to determine what bit values are used to replace predetermined bits of the input address to selectively create a corresponding permutated address. Since no modification to a processor's pipeline is required, various permutation addressing modes may be user-defined and implemented using either a general-purpose processor or a specialized processor.

System having user programmable addressing modes and method therefor

Accurate delay testing of integrated circuits containing memory arrays embedded in combinational logic utilizes actual memory array timing. Actual memory timing signals provide the timing for bypassing the memory in SCAN Mode. The result is that simulated memory accesses during SCAN Mode testing have the same timing as actual memory accesses have during functional mode operation. Thus delay testing during SCAN Mode through paths containing both combinational logic and memory arrays accurately determines path delays.

Scan based path delay testing of integrated circuits containing embedded

A processor (10) has a data cache unit (16) wherein the data cache unit includes a memory management unit (MMU) (32). The MMU contains memory locations within transparent translation registers (TTRs), an address translation cache (40), or a table walk controller (42) which store or generate cache mode (CM) bits which indicate whether a memory access (i.e., a write operation) is precise or imprecise. Precise operations require that a first write operation or bus write instruction be executed with no other operationsnstructions executing until the first operation/instruction completes with or without a fault. Imprecise operations are operations/instruction which may be queued, partially performed, or execution simultaneously with other instructions regardless of faults or bus write operations. By allowing the logical address to determine whether the bus write operation is precise or imprecise, a large amount of system flexibility is achieved.

Data processing system for performing either a precise memory access or

A processor (10) has two modes of operation. One mode of operation is a normal mode of operation wherein the processor (10) accesses user address space or supervisor address space to perform a predetermined function. The other mode of operation is referred to as a debug, test, or emulator mode of operation and is entered via an exception/interrupt. The debug mode is an alternate operational mode of the processor (10) which has a unique debug address space which executes instructions from the normal instruction set of the processor (10). Furthermore, the debug mode of operation does not adversely affect the state of the normal mode of operation while executing debug, test, and emulation commands at normal processor speed. The debug mode is totally non-destructive and non-obtrusive to the 'suspended' normal mode of operation. While in debug mode, the existing processor pipelines, bus interface, etc. are utilized.

Superscalar processor with plural pipelined execution units each unit

A data processing system receives a CLK signal for performing operations internal to a data processor (10). The data processor (10) has a CPU (12) which performs operations in response to the CLK signal. The bus is allowed to operate at a frequency which is less than or equal to the operational frequency of the CLK. The bus clock is typically either equal to the clock in frequency or runs at one-half or one-quarter speed. A CLKEN* signal input to the processor (10) is asserted to indicate an active edge of the external bus clock and synchronize the active edge of the external bus clock with an active edge of CLK to allow an active edge of CLK to perform bus operations which coincide with the active edge of the external bus clock. In another form, an internal counter/control circuit (20) may be used internal to the processor (10) to generate internal CLKEN* signals.

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Phoenix, AZ, United States of America

Daniel M McCarthy