Intel Corporation

Daniel M Lavery

Hong Wang

Perry H Wang

Gerolf F Hoflehner

John P Shen

Kalyan Muthukumar

Milind Baburao Girkar

Xinmin Tian

Shih-wei Liao

Dongkeun Kim

John Thomas Shen

David Sehr

Arvind Krishnaswamy

Steve Shih-wei Liao

Rakesh Ghiya

Christopher J Hughes

Youfeng Wu

Wei Ey Li

Ralph Michael Kling

Jamison D Collins

Jianhui Li

Jean-Francois C Collard

Sanjiv M Shah

Yong-fong Lee

Dong-Yuan Chen

Yihua Jin

Chu-Cheow Lim

Marsha Eng

Wei Li

Abhinav Das

Grant E Haab

Hideki Saito

Geolf F Hoflehner

Robyn A Sampson

Guokai Ma

Saurabh S Shukla

A method and system uses exceptions for code specialization in a system that supports transactions. The method and system includes inserting one or more branchless instructions into a sequence of computer instructions. The branchless instructions include one or more instructions that are executable if a commonly occurring condition is satisfied and include one or more instructions that are configured to raise an exception if the commonly occurring condition is not satisfied.

Method and system using exceptions for code specialization in a computer architecture that supports transactions

A method and system to support scheduling of memory store instructions across atomic regions in binary translation in a processing unit or processor. In one embodiment of the invention, the processing unit has a store buffer that allows store instructions to be issued in different order than the source binary program order but still retire in source binary program order. This facilitates a small atomic region that maps to each iteration of a source binary code and these atomic regions are joined together into a pipelined region. In one embodiment of the invention, the processing unit executes commit instruction(s) once every loop iteration instead of executing the commit instruction(s) once after the loop exit.

Method and apparatus to schedule store instructions across atomic regions in binary translation

Methods and apparatuses for compiler-created helper thread for multi-threading are described herein. In one embodiment, exemplary process includes identifying a region of a main thread that likely has one or more delinquent loads, the one or more delinquent loads representing loads which likely suffer cache misses during an execution of the main thread, analyzing the region for one or more helper threads with respect to the main thread, and generating code for the one or more helper threads, the one or more helper threads being speculatively executed in parallel with the main thread to perform one or more tasks for the region of the main thread. Other methods and apparatuses are also described.

Methods and apparatuses for compiler-creating helper threads for multi-threading

The latencies associated with cache misses or other long-latency instructions in a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform a memory prefetch for the main thread. The instructions for the helper thread are dynamically incorporated into the main thread binary during post-pass operation of a compiler.

Post-pass binary adaptation for software-based speculative precomputation

Various embodiments of the present invention relate to methods and systems for optimizing an intermediate code in a compilation logic. The intermediate code is optimized by performing reassociation in software loops. The intermediate code includes at least one critical recurrence cycle. The performance of reassociation in software loops can reduce a critical recurrence cycle in them, which can speed up their execution. The subject method can include the determination of one or more critical recurrence cycles in a software loop. The method can also include the determination of at least one edge in a critical recurrence cycle, with respect to which reassociation can be performed, if one or more pre-determined criteria are met. The method can further include performing reassociation of a dependee and a dependent of an edge. In an embodiment, when one or more pre-determined criteria are met, the logic of the software loop is maintained after performing reassociation of the dependee and the dependent of the edge. Consequently, the number of cycles in a critical recurrence cycle of the software loop is reduced. The execution time of the software loop is also decreased.

Method and system for performing reassociation in software loops

A method and system for optimizing the execution of a software loop is provided. The method involves the determination of an edge in a critical recurrence cycle in the software loop. The edge is a dependency link between two instructions and contains a dependee and a dependent. The dependee is an instruction that produces a result, and the dependent is an instruction that uses the result. The method further involves performing predicate promotion of at least one of the dependee and the dependent if one or more pre-determined conditions are met.

Method for predicate promotion in a software loop

Disclosed are embodiments of a compiler, methods, and system for resource-aware scheduling of instructions. A list scheduling approach is augmented to take into account resource constraints when determining priority for scheduling of instructions. Other embodiments are also described and claimed.

Resource-aware scheduling for compilers

Methods and apparatuses for thread management for multi-threading are described herein. In one embodiment, exemplary process includes selecting, during a compilation of code having one or more threads executable in a data processing system, a current thread having a most bottom order, determining resources allocated to one or more child threads spawned from the current thread, and allocating resources for the current thread in consideration of the resources allocated to the current thread's one or more child threads to avoid resource conflicts between the current thread and its one or more child threads. Other methods and apparatuses are also described.

Methods and apparatuses for thread management of multi-threading

Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce performance bottlenecks due to memory latency and/or a cache miss. A performance analysis tool is used to profile the software application's resource usage and identifies areas in the software application experiencing performance bottlenecks. Compiler-runtime instructions are generated into the software application to create and manage the helper thread. The helper thread prefetches data in the identified areas of the software application experiencing performance bottlenecks. A counting mechanism is inserted into the helper thread and a counting mechanism is inserted into the main thread to coordinate the execution of the helper thread with the main thread and to help ensure the prefetched data is not removed from the cache before the main thread is able to take advantage of the prefetched data.

Methods and apparatus for reducing memory latency in a software application

Methods and apparatus are disclosed for determining if a user-defined software function is a memory allocation function during compile-time. The methods and apparatus determine if a user-defined function returns a new memory object every time the user-defined function is invoked. In addition, the methods and apparatus determine if the memory objects created by the user-defined function are available outside the scope of the user defined function. If the user-defined function returns a new memory object every time the user-defined function is invoked, and the memory objects created by the user-defined function are not available outside the scope of the user defined function, then the user-defined function is determined to be a memory allocation function. Otherwise, the user-defined function is determined to be a non-memory allocation function.

Methods and apparatus for determining if a user-defined software function is a memory allocation function during compile-time

In one embodiment, the invention provides a method for the processing of instructions. A method which comprises analyzing a dynamic execution trace for a program; identifying at least one stream comprising a plurality of basic blocks in the dynamic execution trace; collecting metrics associated with the at least one stream; and optimizing the at least one stream based on the metrics.

Building inter-block streams from a dynamic execution trace for a program

In one embodiment, disambiguation of memory references, such as structure field accesses, of a computer program is performed. Disambiguation may be effected by identifying pure pointer variables within the computer program and applying at least one disambiguation rule to memory references associated with the pure pointers to determine whether the references are disjoint.

Identifying pure pointers to disambiguate memory references

Instruction-level parallelism in software pipelined loops is exploited by predicting future register rotations. A processor includes an architected current frame marker register and at least one unarchitected frame marker register. Register rotation prediction is achieved by setting the register rotation of future iterations of a software loop to be a function of the unarchitected frame marker registers. True data dependencies remain, but the dependencies caused solely by register renaming are removed. Dynamic predication is used to predicate instructions from future iterations, allowing them to be squashed if dependencies are later found. The register renaming that results from the prediction can be included in instructions in a buffer, or a renaming stage in an execution pipeline can perform the renaming.

Growing community of inventors

Santa Clara, CA, United States of America

Daniel M Lavery