International Business Machines Corporation

Daniel Lewis

Diyanesh B Chinnakkonda Vidyapoornachary

Rahul Rao

Girisankar Paulraj

Arindam Raychaudhuri

Saurabh Chadha

Sumantra Sarkar

Sean Dalton

Adarsh Subramanya

A computer-implemented method includes receiving, by a processor, a physical design block and a physical hierarchy of a chip design of a chip. Further, the method includes extracting, by the processor, one or more features of a macro to be added to the chip design based on a logic synthesis of the chip design. Further, the method includes predicting, by the processor, specifications of the macro to be added to the chip design based on the physical design block, the predicting performed using a pre-trained machine learning model. Further, the method includes using, by the processor, the specifications of the macro to perform a physical synthesis of the chip design to determine a physical layout of the chip.

Dynamic abstract generation and synthesis flow with area prediction

A circuit-cycle fault reproduction system includes a hardware processor configured to execute at least one computing cycle corresponding to a given number instructions. A cycle tracking unit is configured to identify at least one test cycle included in a range of computing cycles starting from at a start cycle and completing at an end cycle. A fail cycle detection unit is in signal communication with the cycle tracking unit. The fail cycle detection unit is configured to identify a failed cycle among the plurality of test cycles based on a cycle difference between the starting cycle and the ending cycle, and to actively modify the range of computing cycles based on a comparison between the cycle difference and a cycle difference threshold value.

Circuit-cycle reproduction

A computer-implemented method for instruction-level tracing for analyzing processor failure includes detecting a failure during operation of a processor circuit. The method further includes parsing a miscompare trace to determine a plurality of opcodes executed by the processor prior to the failure. The method further includes generating a workload comprising a set of opcodes by filtering the set of opcodes from the miscompare trace. The method further includes performing a consistency check of the workload to determine a commit ratio of the workload, the commit ratio indicative of a number of times the failure occurs when the workload is executed a predetermined number of times. The method further includes using the workload for debugging the failure based on the commit ratio being above a predetermined threshold.

Instruction level tracing for analyzing processor failure

Managing system memory allocation according to a thermal profile defining memory segment policies according to power, performance, and thermal requirements, selecting a defined memory segment policy, implementing a system workload according to the memory segment policy and deploying the system workload according to the implemented memory segment policy.

Thermally aware memory management

Circuitry including a logic circuitry portion and a delay circuitry portion, with the circuitry having the following features: (i) the logic circuitry is designed to receive a set of input signals including a first input signal and a second input signal; and (ii) the delay circuitry portion includes a transistor connected so that the first input signal gates the second input signal. In some embodiments, the first and second input signals are chosen because it is expected that the second input signal will arrive at the circuitry before the first input signal so that the gating of the second signal by the first signal will cause the logic circuitry portion to receive the first and second signals at substantially the same time. Also, circuitry where a first output signal from a logic circuitry portion is gated by a second output signal.

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Bengaluru, India

Daniel Lewis