Texas Instruments Corporation

Daniel Lee Corum

Donald L Plumton

Douglas A Prinslow

Stanton Petree Ashburn

Abha Singh Kasper

Harold C Waite

Eric D Rullan

Taylor Jon Lowry

Methods and devices for mapping logical addresses to physical locations on an integrated circuit die are disclosed herein. An embodiment of the method includes fabricating a die, where the die has a plurality of bits that are electrically accessible by way of logical addresses. A plurality of bits have known defects that form a predetermined fault pattern at a predetermined location on the die. The bits are tested by using the logical addresses, wherein the testing yields data as to the functionality of the bits. The test results are searched for the predetermined fault pattern. The physical locations of the defective bits constituting the predetermined fault pattern are correlated with their logical addresses based on the location of the predetermined fault pattern.

Methods and devices for determining logical to physical mapping on an integrated circuit

Detecting a defect of an integrated circuit includes illuminating an integrated circuit with an optical beam. The integrated circuit includes a substrate, a dielectric layer disposed outwardly from the substrate, and a sequence of metal links disposed within the dielectric layer. An end metal link of the sequence of metal links is grounded. A change of relative brightness of the dielectric layer proximate to the sequence of metal links is detected. The change of relative brightness comprises a difference between a first brightness associated with a first metal link and a second brightness associated with a second metal link coupled to the first metal link. The change of relative brightness is associated with a defect of the integrated circuit.

Detecting a defect of an integrated circuit

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Richardson, TX, United States of America

Daniel Lee Corum