Bae Systems Information and Electronic Systems Integration Inc.

International Business Machines Corporation

Daniel L Stanley

David D Moser

Jon F Hauris

Michael J Graziano

Dale A Rickard

Joseph R Marshall, Jr

Richard J Ferguson

Tate J Keegan

Timothy B Brodnax

Steven A King

Sheldon L Grass

Christopher N Peters

Joshua C Schabel

John Stanley Bialas, Jr

Jason F Ross

Johnny James LeBlanc

Bryan Keith Bullis

Richard Brosh

Alan F Dennis

Michael J Frack

Elizabeth J Williams

John T Matta

Mark R Shaffer

Robert L Schoenike

Jonathan W Edwards

Eric H Liu

Todd W Montgomery

Clark J Spencer

Umair Aslam

Christopher T Scioscia

Angelica Sunga

A secure system includes a data port, a network on chip (NoC) module, a processor communicatively coupled to the NoC module, a communication interface operatively coupled to the processor and to the data port, an electronic field-programmable gate array (eFPGA) configuration module operatively coupled to the NoC module, and a clock operatively coupled to the NoC module. In a first modality, the communication interface is at least partially disabled. In a second modality, the communication interface is at least partially disabled, boundary scan operations are disabled, a RESET signal is held in a constant state, and/or redacted code is rendered inoperable. In a third modality, the communication interface is at least partially enabled to send and receive commands and data via the data port, the boundary scan operations are enabled, the RESET signal is not held in the constant state, and/or the redacted code is operable.

Secure semiconductor and system design

A system that includes a plurality of encapsulation blocks having a plurality of digital signal processing (DSP) blocks provided with preconfigured logic functions and a plurality of pacing control networks operatively connected with the plurality of DSP blocks. The system also includes a streaming cross bar operatively connected with each encapsulation block of the plurality of encapsulation blocks. Each encapsulation block of the plurality of encapsulation blocks includes a DSP block of the plurality of DSP blocks and a pacing control network of the plurality of the pacing control networks. Each DSP block of the plurality of DSP blocks is independently and separately connected with the streaming cross bar via the plurality of pacing control networks.

DSP eco system scalable with obfuscation

An encapsulation block for a digital signal processing (DSP) block. The encapsulation block includes DSP block having an input terminal, an output terminal, and an input clock. The encapsulation block also includes pacing control network operatively connected with the input terminal, the output terminal, and the input clock of the DSP block. The input terminal of the DSP block is configured to receive a samples-in data stream inputted at a predefined clock period defined by the input clock. The output terminal of the DSP block is configured to receive a samples-out data stream outputted at a predefined paced parameter. The pacing control network is configured to control data flow at the samples-in data stream and the samples-out data stream independently of the DSP block.

DSP encapsulation

Techniques are provided for a radiation hardened memory system. A memory system implementing the techniques according to an embodiment includes a redundancy comparator configured to detect differences between data stored redundantly in a first memory, a second memory, and a third memory. The redundancy comparator is further configured to identify a memory error based on the detected differences. The memory system also includes an error collection buffer configured to store a memory address associated with the memory error, and a memory scrubber circuit configured to overwrite, at the memory address associated with the memory error, erroneous data with corrected data. The corrected data is based on a majority vote among the three memories. The memory system further includes a priority arbitrator configured to arbitrate between the memory scrubber overwriting and functional memory accesses associated with software execution performed by a processor configured to utilize the memory system.

Triple modular redundancy (TMR) radiation hardened memory system

A clock phase control circuit includes a clock input gate module, first and second shift register divider modules, and a multiplexer. The clock input gate module is configured to produce, based on an oscillating input clock signal, first and second intermediate clock signals. The first shift register divider module is configured to produce at least one first phase clock signal based on the first intermediate clock signal, where the at least one first phase clock signal has a different frequency than the first intermediate clock signal. The second shift register divider module is configured to produce at least one second phase clock signal based on the second intermediate clock signal, where the at least one second phase clock signal has a different frequency than the second intermediate clock signal. The multiplexer is configured to produce an output clock signal by selecting one of the first or second phase clock signals.

Clock phase control

A power distribution device includes an input, an output, a power switch controller, and a voltage isolation device. The power distribution device includes, and is designed to provide power to, for example, non-radiation-tolerant or non-radiation hardened components for use in low Earth orbit (LEO) missions. The input is configured to receive power from a power source. The output is configured to provide the power to an electrical load. The power switch controller is configured to selectively operate the power distribution device in a first mode responsive to a first event, and to selectively operate the power distribution device in a second mode responsive to a second event. The voltage isolation device includes a plurality of switches configured, in the first mode, to pass the power between the input and the output, and, in the second mode, to interrupt the passage of the power between the input and the output.

Power distribution device

An MCM-HIC device flexibly adds enhanced features to a VLSI 'core' IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one 'chiplet' that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or 'mixed' chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.

Multi-chip hybrid system-in-package for providing interoperability and other enhanced features to high complexity integrated circuits

A computer device includes an interface board, a plurality of peripheral component interface (PCI) busses on the interface board, and a plurality of device card connectors carried by the interface board. The plurality of device card connectors include at least one first device card connector coupled to first and second PCI busses synchronous with one another, and at least one second device card connector coupled to the second PCI bus and to a third PCI bus asynchronous with the second PCI bus. The PCI busses are thus connected so that the PCI busses may be added in groups according to the number of device card connectors supported by the interface board, and not by the loading constraints of the PCI busses themselves. By defining both synchronous and asynchronous device card connectors, device cards requiring either synchronous or asynchronous communications may be utilized by the computer device. Each device card includes an interface bridge for connecting to a respective asynchronous or synchronous device card connector.

Computer device having multiple linked parallel busses and associated method

A communications adapter receives and transmits simultaneously packet and/or isochronous data between two interfaces; a network and a host bus system. The adapter stores the isochronous and packet data in receive and transmit queues configured in a FDDI RAM buffer. A controller manages the transfers of the data into and out of the queues. A local bus interacts with the system to provide descriptors of addresses in the system for transfers of data out of the queues to the system or the network. The controller is programmable to provide a variable threshold for the transfer of data between the queues and the system or the network. A systems interface unit handles the transfer of data to/from the system and allows data to bypass the queues and directly access the system or the network.

Multimedia communication apparatus and methods

Multimedia system and method of controlling data transfer between a host

Communication apparatus and methods having P-MAC, I-MAC engines and

A fault tolerant processing system including a prediction RAM employs a Lock Step Compare routine. The method developed allows the processing system to recover from single event upsets. In initialization, the branch prediction RAM is set to a known value. An engineering balance is achieved by adding logic to detect a branch RAM error and incurring the delay of re-initializing the entire RAM only when a RAM error has been detected.

Synchronizing a prediction RAM

A fault-tolerant computer system having shadow registers for storing the contents of a primary array into a shadow array at the completion of a stored instruction execution. This is accomplished in one clock cycle with all registers being shadowed simultaneously. During rollback of execution steps for a checkpoint retry, the shadow register files provide a signal cycle unload of the shadow array into the primary array. LSSD latches are used in the shadow register file.

Shadow register file for instruction rollback

A method of switching multimedia data streams in response to requests to allocate or deallocate a user on a network receiving those data streams is herein described. The data streams are transmitted in master cycles, portions of each master cycle being allocated to each user. The relationship between the user and the portion of the master cycle is kept track of by means of a matrix method.

Growing community of inventors

Manassas, VA, United States of America

Daniel L Stanley