Texas Instruments Corporation

National Semiconductor Corporation

Daniel L Simon

Mark Kuhns

William Otis Keese

Sasa Radovanović

An adaptive impedance matching module having an adjustable impedance matching network with an input for receiving an RF power source and an output to be connected to an antenna, and first and second voltage measurement device configured to sense a voltage at respective first and second nodes on the impedance matching network. A network adjuster circuit is provided to switch the impedance matching network between a first state where first and second voltages are sensed on the respective first and second nodes and a second state where third and fourth voltages are sensed on the respective first and second nodes. Processing circuitry is provided which determines the matched load impedance based upon the first, second, third and fourth sensed voltages and including matching adjustment circuitry configured to adjust the matching impedance in the event the matched load impedance differs from a target load impedance by more that a predetermined amount.

RF impedance detection using two point voltage sampling

A circuit for reducing and offsetting the voltage swing of a differential pre-drive circuit. The circuit includes a first H-bridge of transistors receiving a differential pair of input signals. A swing resister is coupled to the H-bridge for reducing a voltage swing of the differential pair of input signals. The reduced swing is generated as a differential pair of output signals. Also, the differential pre-drive circuit includes an offset resistor that is coupled to the H-bridge. The offset resistor acts to offset the differential pair of output signals. As such, the differential pair of output signals having reduced swing and offset as applied to gates of output transistors in an output stage allow the output transistors to remain in the saturation operating state.

Reduced swing differential pre-drive circuit

A system and method for performing output clock phase smoothing. A phase smoothing circuit is described and includes a numerically-controlled oscillator (NCO) configured to produce a plurality of NCO clock pulses at a selectable frequency that is based on an input clock. Edges of the plurality of NCO clock pulses are aligned to edges of the input clock. A phase error calculation module is coupled to the NCO and is configured to generate a corresponding phase error for each of the plurality of NCO clock pulses. A clock phase selectable delay is coupled to the phase error calculation module and is configured to adjust each of the plurality of NCO clock pulses according to the corresponding phase error to generate an output clock at the selectable frequency that are phase-adjusted to more closely match an ideal output clock phase. Edges of the output clock need not necessarily align to the edges of the input clock.

Numerically controlled oscillator (NCO) output clock phase smoothing

A circuit for controlling a duty cycle of a clock signal. The circuit includes a duty cycle control loop that includes a voltage-to-duty cycle (V-to-DC) converter, an output driver, a duty-cycle-to voltage (DC-to-V) converter, and an operational amplifier. The V-to-DC converter receives an input clock signal. The output driver is coupled to the V-to-DC converter and provides an output clock signal that is associated with a duty cycle distortion value. The DC-to-V converter converts the output clock signal to an average voltage. The operational amplifier amplifies an error between the average voltage and a reference voltage. The error is fed back to the V-to-DC converter through a negative feedback loop, wherein the V-to-DC converter adjusts a duty cycle of the input clock signal based on the error.

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Glendale, AZ, United States of America

Daniel L Simon