Altera Corporation

Daniel L Reilly

Phong T Cao

Adam J Wright

Yoke Mooi Lee

The present invention is directed to a method and system for rapidly identifying physical locations of manufacturing defects on the surface of a semiconductor die. The method and system first retrieve information about an electrical failure from an IC's electrical test result and then identify a set of electrical elements from the IC's layout design including a start resource and an end resource. Next, the method and system identify a physical signal path between the start resource and the end resource using the IC's layout design. Finally, the method and system examine a corresponding region on the semiconductor die that covers the physical signal path for manufacturing defects that may be responsible for the electrical failure.

Method and system for rapidly identifying silicon manufacturing defects

A tool for testing an integrated circuit is provided. The tool includes a vector execution engine, a vector image generation engine and a vector display engine. The vector execution engine applies test patterns to the integrated circuit and captures error data being output from the test patterns. The vector image generation engine generates a file of expected output from the application of the test patterns to the integrated circuit. It should be appreciated that the generation of the vector image file occurs offline from the testing by the vector execution engine. The tool also includes a vector display engine allowing identification of vectors including error data. In one embodiment, a timestamp is associated with the vectors of the vector image file and a timestamp is associated with the vectors of the error data. A method for testing an integrated circuit and a graphical user interface are also included.

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Mountain View, CA, United States of America

Daniel L Reilly