Other

Control Data Corporation

Pioneer Research, Inc.

Control Data Systems, Inc.

Daniel L Nay

John T Ralph

Darryl K Korn

Richard Williams

James K Berger

Frank T Brady

David Shick

Colin M Searle

John Meyer

Guy B Beckley

Jon C Wilson, Deceased

Ivan Jelenek

In a computer system that contains plural computer resource elements, such as multiple processor and memory units, with those elements communicating digital information over a common communications bus, high communications bus efficiency is achieved. An interface permits each of said processor and memory elements to individually and independently access either the data bus, without busying the address bus, or the address bus without busying the data bus, with bus access being limited to a fixed interval of time. Different ones of said processor and memory units may thus simultaneously transfer digital information over the respective address and data bus. The foregoing system includes a bus contention and priority protocol to eliminate the possibility of data collision and includes identification lines for identifying each processor element accessing the bus.

Processor communication bus

Data messages are transmitted between host data processors and a communications processor. Data messages from a communications processor are transformed for the host processor to which the message is assigned. Data messages from a host processor are transformed for the communications processor. Protocol is established between (a) untransformed data messages from the communications processor and transformed data messages for the communications processor, and (b) untransformed data messages from each host processor and transformed data messages for each host processor. A device interface connects a plurality of host processors to a plurality of buses, each bus being connected to one communications processor. The device interface handles the protocol, transformation and control function in parallel so that messages between a given host processor and terminal connected to a communications processor are processed through a device interface. The result is that user terminals and host applications are managed as 'pools' of logical devices with dynamic session assignment.

Communications network

A computer memory system which includes a relatively slow access main memory unit and a relatively fast access smaller cache memory unit, the memory units being controlled by a central processing unit, and which further includes control circuitry for accessing the cache memory unit for all data words addressed by the central processing unit, and when an addressed word is not available in the cache memory, automatically transferring the addressed word from the main memory to the cache memory, the control being such that when such an addressed word is transferred from the main memory to the cache memory, adjacent words in the main memory are simultaneously transferred to the cache memory to be readily available to the central processor unit.

Computer memory system

A system by which a number of central processing units (CPU's) may be used completely independently of one another, and yet by which any CPU within the system may communicate with any other CPU in the system. The implementation of the system requires each CPU to be physically connected only to its own bus and to the bus of one other CPU even if there are many CPU's and buses in the system. This enables each CPU in the system to have access to all of the buses of all of the other CPU's in the system.

Multi-level bus access for multiple central processing unit

A data communications apparatus transfers data between two channels, the data formats of each being incompatible with the other. Index registers receive index addresses from each channel to access a pointer in a pointer RAM. The pointer addresses a data location in a data RAM to permit data to be stored or read from either channel at the data transfer rate and byte size for that channel. Registers are provided between each RAM and at least one of the channels to concatenate smaller byte words for transfer between the RAMs and the one channel. Counter apparatus drives the pointer RAM to access successive locations in the data RAM, as desired.

Data communication apparatus

A programmable servo pattern generator for use in a magnetic disc drive servowriter system. The servo pattern generator of the present invention stores a multiplicity of different servo patterns in a convenient user-oriented format, and it provides high frequency pulse trains of NRZ data representing the different servo patterns. These different servo patterns are derived from the pattern generator of the invention as required and in the particular formats to be written into the magnetic disc drives of the same or different manufacturers.

Growing community of inventors

Palos Verdes, CA, United States of America

Daniel L Nay