Diamond Multimedia Systems, Inc.

Sigmatel, Inc.

Daniel L Moore

Michael Hudson

An apparatus and method to synchronize devices in a network to a sub-millisecond timing accuracy. In a first embodiment, the transmission of data is synchronized between a first source device and destination devices communicatively coupled to a network. In a second embodiment, data is deterministically transmitted between a first source device and destination devices communicatively coupled to a network. In a third embodiment, a deterministic network synchronizes the transmission of data between a first source device and destination devices coupled to a network.

Apparatus and method to synchronize multimedia playback over a network using out-of-band signaling

A system is disclosed that includes a plurality of processors, which in some embodiments include DSPs and other microprocessors, and a distributed uniform memory. The distributed uniform memory is subdivided into a plurality of addressable memory spaces each of which are respectively primarily associated with one of the processors in the plurality of processors. At least an addressably contiguous portion of the addressable memory space primarily associated with one processor is mapped into the addressable memory space primarily associated with another processor. Thus, a processor will have access to the addressable memory space primarily associated with another processor, but will have such access independent of the load and timing requirements of the other processors.

Signal processing system with distributed uniform memory

A system is disclosed that includes a first processor, which in some embodiments includes a DSP, and a first memory pool and a second memory pool. The second memory pool is primarily associated with the DSP and stores code that is available for execution by the DSP. A plurality of code modules are stored in the first memory pool, which in some embodiments is associated with a second processor. The code modules are individually and dynamically swapped into the first memory pool, which in some embodiments is not large enough to simultaneously store all of the code modules. In some instances, the dynamic code module swapping is done at the direction of a second processor, which is aware of the state of the DSP execution. In other instances, the dynamic code module swapping is done at the direction of the DSP. In each instance, dynamic code swapping is performed in a manner that minimizes or eliminates any halts in DSP instruction execution.

DSP code swapping with continuous DSP execution

A system in accordance with the invention allows a signal processing system to be configured to perform almost any signal processing function. Such a system includes a redefinable signal processing subsystem and a function-specific module. The system can be defined to perform a particular function by attaching a function-specific module to the redefinable subsystem and downloading function-defining code into the subsystem. The redefinable subsystem includes at least a DSP, a local memory interface, a host interface, and a function module interface. The function-specific module includes at least a subsystem interface, an identifier storage unit, a signal format converter, and a communication adapter. In operation, after a function-specific module is coupled to the subsystem, the subsystem receives a function identifier from the identifier storage unit on the module. The subsystem then requests and receives function-defining code from a host. The function-defining code is maintained in an auxiliary memory and portions thereof are periodically distributed to a local memory, coupled to the subsystem via the local memory interface, at which time the code modules are available for execution by the DSP. When engaged in communications, the module receives data from the DSP through a high speed digital serial channel. The module converts the data format with its signal format converter and then passes the converted data to the communication adapter. The communication adapter conditions the data for conveyance to an external communication signal delivery media.

Redefinable signal processing subsystem

Method of configuring a functionally redefinable signal processing system

The present invention is directed toward the low latency transport of signals demanding rapid communication. In modems utilizing an error-correcting protocol, messages are generally buffered and sent as a data packet. However, the method in accordance with the invention provides for transport of low latency messages without buffering or formation of a data packet, minimizing signal latency. In addition, modems operating in accordance with the invention maintain compatibility with other modems.

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Vancouver, WA, United States of America

Daniel L Moore