Lockheed Martin Corporation

Unisys Corporation

Loral Corporation

Daniel L Heflin

Gary V Layton

In a control system for controlling a very large number of remotely located input and output devices there is provided a novel control system having a single CPU coupled through a host interface module to a data and control transmission line. The host interface module on the transmission line receives information from and transmits information to a plurality of secondary interface modules having node addresses. The information being transmitted on the control and data transmission line is formatted to comprise one or two data bytes, an address and command byte, and an error checking byte to permit operation in a noisy electrical environment. Each said interface modules is further provided with high speed logic and an address counter for identifying node addresses and carrying out the commands and transmission of data without the requirement for software or firmware.

Modular interface devices for a distributed input/output system

Apparatus and method synchronize one or more digital clock signals from separate oscillators, to another clock oscillator via a common non-continuous signal, and provide error signals to indicate when one or more oscillators are out of tolerance.

Synchronizer and method therefor

A system for sensing the state or condition of a very large number of interconnection points in real time in electrical context with other points in a system. The system has a plurality of multiple interconnect sense modules having a plurality of interconnection sensing points for coupling to other points in the system. The system further has a transmitter/receiver in the module for each interconnection point to be sensed. The system further has an address generator counter for generating a unique address at each transmitter/receiver during a unique time period identifying each transmitter/receiver. A logic controller is provided with inputs from each of the receivers of the transmitter/receiver for sensing the state of the receivers at its unique time period. An encoder is coupled to the output of the logic controller for generating information indicative of the interconnection of two interconnection points during each one of the unique time periods. The output of the encoder is coupled to a buffer. The buffer is coupled to a CPU and to the address counter for receiving information indicative of the connection between any interconnection point and any other interconnection point in real time.

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Front Royal, VA, United States of America

Daniel L Heflin