Luxtera, Inc.

Other

Cisco Technology, Inc.

Lutxtera, Inc.

Daniel Kucharski

Sherif Abdalla

Thierry J Pinguet

Brian Welch

John Andrew Guckenberger

Attila Mekis

Gianlorenzo Masini

Steffen Gloeckner

Kosei Yokoyama

Lawrence Cary Gunn, Iii

Peter De Dobbelaere

Roger Koumans

Thiruvikraman Sadagopan

Behnam Analui

Peter DeDobbelaere

John Guckenberger

Guckenberger John

Methods and systems for encoding multi-level pulse amplitude modulated signals using integrated optoelectronics are disclosed and may include generating a multi-level, amplitude-modulated optical signal utilizing an optical modulator driven by first and second electrical input signals, where the optical modulator may configure levels in the multi-level amplitude modulated optical signal, drivers are coupled to the optical modulator; and the first and second electrical input signals may be synchronized before being communicated to the drivers. The optical modulator may include optical modulator elements coupled in series and configured into groups. The number of optical modular elements and groups may configure the number of levels in the multi-level amplitude modulated optical signal. Unit drivers may be coupled to each of the groups. The electrical input signals may be synchronized before communicating them to the unit drivers utilizing flip-flops. Phase addition may be synchronized utilizing one or more electrical delay lines.

Method and system for encoding multi-level pulse amplitude modulated signals using integrated optoelectronic devices

Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses. The devices may be fabricated on semiconductor-on-insulator (SOI) wafers utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.

Method and system for monolithic integration of photonics and electronics in CMOS processes

Methods and systems for split voltage domain transmitter circuits may include a two-branch output stage including a plurality of CMOS transistors, with each branch of the two-branch output stage comprising two stacked CMOS inverter pairs. The two stacked CMOS inverter pairs of a given branch are configured to drive a respective load, in phase opposition to the other branch. A pre-driver circuit is configured to receive a differential modulating signal and output, to respective inputs of the two stacked CMOS inverters, two synchronous differential voltage drive signals having a swing of half the supply voltage and being DC-shifted by half of the supply voltage with respect to each other. The load may include a series of diodes that are driven in differential mode via the drive signals. An optical signal may be modulated via the diodes.

Method and system for split voltage domain transmitter circuits

Methods and systems for split voltage domain transmitter circuits are disclosed and may include a two-branch output stage including a plurality of CMOS transistors, each branch of the two-branch output stage comprising two stacked CMOS inverter pairs from among the plurality of CMOS transistors; the two stacked CMOS inverter pairs of a given branch being configured to drive a respective load, in phase opposition to the other branch; and a pre-driver circuit configured to receive a differential modulating signal and output, to respective inputs of the two stacked CMOS inverters, two synchronous differential voltage drive signals having a swing of half the supply voltage and being DC-shifted by half of the supply voltage with respect to each other. The load may include a series of diodes that are driven in differential mode via the drive signals. An optical signal may be modulated via the diodes.

A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between a first die and a second die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

Method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems

Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include in an optoelectronic transceiver comprising photonic and electronic devices from two complementary metal-oxide semiconductor (CMOS) die with different silicon layer thicknesses for the photonic and electronic devices, the CMOS die bonded together by metal contacts: communicating optical signals and electronic signals to and from said optoelectronic transceiver utilizing a received continuous wave optical signal as a source signal. A first of the CMOS die includes the photonic devices and a second includes the electronic devices. Electrical signals may be communicated between electrical devices to the optical devices utilizing through-silicon vias coupled to the metal contacts. The metal contacts may include back-end metals from a CMOS process. The electronic and photonic devices may be fabricated on SOI wafers, with the SOI wafers being diced to form the CMOS die.

A method and system for implementing high-speed electrical interfaces between semiconductor dies in optical communication systems are disclosed and may include communicating electrical signals between an electronics die and an optoelectronics die via coupling pads which may be located in low impedance points in Tx and Rx paths. The electrical signals may be communicated via one or more current-mode, controlled impedance, and/or capacitively-coupled interfaces. The current-mode interface may include a cascode amplifier stage split between source and drain terminals of transistors on the dies. The controlled-impedance interfaces may include transmission line drivers on a first die and transmission lines on a second die. The capacitively-coupled interfaces may include capacitors formed by contact pads on the dies. The coupling pads may be connected via one or more of: wire bonds, metal pillars, solder balls, or conductive resin. The dies may comprise CMOS and may be coupled in a flip-chip configuration.

Method and system for implementing high-speed interfaces between semiconductor dies in optical communication systems

Methods and systems for a photonically enabled complementary metal-oxide semiconductor (CMOS) chip are disclosed and may comprise in an integrated circuit comprising a driver: amplifying a received signal in a plurality of partial voltage domains, and generating the partial voltage domains by controlling a voltage domain boundary value between two partial voltage domains utilizing a differential amplifier that samples an output voltage of a cascade amplifier that is an input to the driver and controls a current supplying said cascade amplifier. A series of diodes may be driven in differential mode via the amplified signals. An optical signal may be modulated via the diodes, which may be integrated in a Mach-Zehnder modulator or a ring modulator. The diodes may be connected in a distributed configuration. The amplified signals may be communicated to the diodes via transmission lines, which may be even-mode coupled.

Methods and systems for encoding multi-level pulse amplitude modulated signals using integrated optoelectronics are disclosed and may include generating a multi-level, amplitude-modulated optical signal utilizing an optical modulator driven by two or more of a plurality of electrical input signals. The optical modulator may configure levels in the multi-level amplitude modulated optical signal. Drivers may be coupled to the optical modulator, and the plurality of electrical input signals may be synchronized before being communicated to said drivers. Two or more of said plurality of electrical input signals may be selected utilizing one or more multiplexers. The one or more multiplexers may select an electrical input or a complement of the electrical input. Phase addition may be synchronized in a plurality of optical modulator elements in the optical modulator utilizing one or more electrical delay lines. The optical modulator may be integrated on a single substrate.

Methods and systems for a photonically enabled complementary metal-oxide semiconductor (CMOS) chip are disclosed and may comprise in an integrated circuit comprising a driver: amplifying a received signal in a plurality of partial voltage domains, and generating the partial voltage domains in a domain splitter in the driver. A voltage domain boundary value between two partial voltage domains may be controlled utilizing a differential amplifier that samples an output voltage of a cascade amplifier that is an input to the driver and controls a current supplying said cascade amplifier. A series of diodes may be driven in differential mode via the amplified signals. An optical signal may be modulated via the diodes, which may be integrated in a Mach-Zehnder modulator or a ring modulator. The diodes may be connected in a distributed configuration. The amplified signals may be communicated to the diodes via transmission lines, which may be even-mode coupled.

Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices with at least a portion of each of the wafers bonded together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Monolithic integration of photonics and electronics in CMOS processes

Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

Growing community of inventors

Carlsbad, CA, United States of America

Daniel Kucharski