Qualcomm Incorporated

Other

Daniel Keyes Butterfield

Yi Tang

Harinath Garudadri

Jeremy Darren Dunworth

Bo Sun

Somdeb Majumdar

Saed G Younis

Peiyuan Wang

Sanjay Marthanda

Lindsay A Weaver, Jr

Franklin Peter Antonio

Volodimir Slobodyanyuk

Seyfollah Seyfollahi Bazarjani

Steven C Ciccarelli

Kamran Moallemi

Aspects generally relate to reducing delay, or phase jitter, in high speed signals transmission. Variations in power supply to ground potential changes the amount of delay introduced by transmit circuitry into the signal being transmitted, resulting in jitter, or phase noise, in the transmitted signal. To reduce phase jitter, or phase noise, aspects disclosed include a variable impedance circuit coupled to the signal distribution network, the impedance level of the variable impedance circuit is adjusted in response to variation in the supply to ground potential, such that the delay introduced by the impedance compensates for changes in the delay due to variations in supply to ground potential, resulting in substantially constant delay.

Supply compensated delay cell

An example method for use with a LIDAR system includes assigning a firing time of a laser included in the LIDAR system. The assignment of the firing time includes: (i) receiving a universal clock signal at the LIDAR system, where the universal clock signal common to one or more other LIDAR systems; (ii) synchronizing a system clock of the LIDAR system to the universal clock signal to generate a synchronized clock signal; and determining the firing time based on the synchronized clock signal to reduce interference with the one or more other LIDAR systems. The method also includes firing the laser at the firing time.

Timing synchronization of LIDAR system to reduce interference

One feature pertains to an apparatus that includes a first stage track and hold circuit that subsamples a receive equalizer output of a receive equalizer, and a second stage track and hold circuit that generates a first signal representative of an average voltage value of a logical value at the receive equalizer output when a high frequency bit pattern is detected, and a second signal representative of an average voltage value of the logical value at the receive equalizer output when a steady state bit pattern is detected. The apparatus further includes a comparator circuit that generates a comparator output signal that indicates which of the first signal and the second signal has a greater magnitude, and a processing circuit that generates equalizer tuning signals based on the comparator output signal to adjust parameters of an equalizer that affects the receive equalizer output.

Serial link adaptive equalization using track and hold circuits

The present disclosure includes switched capacitor transmitter circuits and methods. In one embodiment, the present disclosure includes a plurality of switched capacitor transmitter circuits coupled to inputs of an inductive network. The inductive network combines voltages from the switched capacitor transmitter circuits to produce a combined voltage on an output. In another embodiment, a digital data signal is thermometer encoded and a negative thermo-encoded signal is bit order reversed to control capacitors in a switched capacitor transmitter circuit.

Switched capacitor transmitter circuits and methods

The present disclosure includes switched capacitor transmitter circuits and methods. In one embodiment, a digital data signal is thermometer encoded and a negative thermo-encoded signal is bit order reversed to control capacitors in a switched capacitor transmitter circuit. In another embodiment, the present disclosure includes a plurality of switched capacitor transmitter circuits coupled to inputs of an inductive network. The inductive network combines voltages from the switched capacitor transmitter circuits to produce a combined voltage on an output.

An apparatus and method for communications are disclosed. The apparatus may include an a quantizer having three levels, and a switching power amplifier configured to drive a load having first and second terminals, wherein the switching power amplifier is further configured to switch the first and second terminals between first and second power rails only if the output from the quantizer is at one of the three levels.

Switching power amplifier for quantized signals

A hardware-efficient transceiver. The transceiver includes a digital circuit for converting baseband signals to intermediate frequency signals. A signal source provides a first periodic signal of a first frequency. A direct digital synthesizer provides a second periodic signal of a second frequency from the first periodic reference signal. An upconverter circuit digitally upconverts the baseband signals to digital intermediate frequency signals using the second periodic signal A digital-to-analog converter converts the digital intermediate frequency signals to analog intermediate frequency signals using the first periodic signal. In the transceiver implementation, the digital circuit upconverts a first transmit signal from a first frequency to a second frequency in response to the second periodic signal and provides a digital transmit signal in response thereto. A second circuit is provided for converting the digital transmit signal to an analog transmit signal. Transmit and receive circuitry are provided for transmitting the analog transmit signal and receiving an analog receive signal, respectively. In a specific embodiment, the analog receive signal is digitally downconverted to provide a digital receive signal in response to a second periodic signal. A significant feature of the invention resides in the provision of the first and second periodic signals with a single local oscillator. A direct digital synthesizer is included for generating one of the reference signals from the output of the local oscillator. The transmit circuit includes a delta-sigma digital-to-analog converter having the first periodic signal as an input The delta-sigma digital-to-analog converter has a low-bit digital-to-analog converter and a delta-sigma modulator. In the illustrative embodiment, the low-bit digital-to-analog converter is a 1-bit digital-to-analog converter and the delta-sigma modulator is a sixth order delta-sigma modulator. The delta-sigma modulator includes amplifiers with approximately the following gains: 3/2, &minus;3/4, 1/8.

Hardware-efficient transceiver with delta-sigma digital-to-analog converter

An inventive high-resolution Delta-Sigma analog-to-digital converter using a Continuous-Time implementation having suppressed sensitivity to clock jitter. The inventive method and apparatus suppresses the sensitivity to jitter by the square of the oversampling ratio when compared to current Continuous-Time implementations of Delta-Sigma modulators. The present invention eliminates the clock jitter disadvantage between sampled-data and Continuous-Time implementations of Delta-Sigma modulators. The present invention preferably includes a digital-to-analog converter that ensures that the integral of an output voltage is constant over a clock duty cycle regardless of clock jitter. The digital-to-analog converter preferably includes at least two switches and a capacitor. A first switch is used to charge the capacitor and a second switch is used to discharge the capacitor. Each switch is controlled by a clock phase wherein the sum of the two phases equals the clock duty cycle.

Method and apparatus for eliminating clock jitter in continuous-time Delta-Sigma analog-to-digital converters

A receiver comprising a sigma-delta analog-to-digital converter (.SIGMA..DELTA. ADC) can be utilized in one of four configurations, as a subsampling bandpass receiver, a subsampling baseband receiver, a Nyquist sampling bandpass receiver, or a Nyquist sampling baseband receiver. For subsampling .SIGMA..DELTA. receivers, the sampling frequency is less than twice the center frequency of the input signal into the .SIGMA..DELTA. ADC. For Nyquist sampling .SIGMA..DELTA. receivers, the sampling frequency is at least twice the highest frequency of the input signal into the .SIGMA..DELTA. ADC. For baseband .SIGMA..DELTA. receivers, the center frequency of the output signal from the .SIGMA..DELTA. ADC is approximately zero or DC. For bandpass .SIGMA..DELTA. receivers, the center frequency of the output signal from the .SIGMA..DELTA. ADC is greater than zero. The sampling frequency can be selected based on the bandwidth of the input signal to simplify the design of the digital circuits used to process the output samples from the .SIGMA..DELTA. ADC. Furthermore, the center frequency of the input signal can be selected based on the sampling frequency and the bandwidth of the input signal. The .SIGMA..DELTA. ADC within the receiver provides many benefits.

Receiver with sigma-delta analog-to-digital converter for sampling a

An apparatus and method for providing communication of information between a truck tractor and trailer via existing truck wiring. At least one transmitter is located in each trailer for generating a unique identification signal representative of trailer identification information corresponding to the trailer in which the transmitter is located, modulating the identification signal, and providing the modulated identification on an existing truck power bus coupling the tractor and trailer. A receiver is located in the tractor for receiving each modulated identification signal on the power bus, demodulating each modulated identification signal and providing each demodulated identification signal to a mobile communications terminal located in the tractor for transmission to a central facility. The system may further include the transmission of trailer status or load status information by the transmitter to the receiver in a similar manner as the identification information.

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San Diego, CA, United States of America

Daniel Keyes Butterfield