Synopsys, Inc.

Daniel Keith Weinlader

John Theodore Stonick

David Andrew Yokoyama-Martin

Jeffrey Lee Sonntag

Jianping Wen

Skye Wolfer

James P Flynn

Junqi Hua

Robert Beverly Lefferts

Christopher Scott Jones

Richard H Steeves

Ross Segelken

Dino Anthony Toffolon

Jasjeet Singh

Aaron Joseph Caffee

Circuitry to facilitate testing of serial interfaces is described. Specifically, some embodiments of the present invention facilitate testing the clock and data recovery functionality of a receiver. A serial interface can include a multiplying phase locked loop (MPLL) clock generator, a transmitter, and a receiver. The MPLL clock generator can generate a first clock signal and a second clock signal, and can vary a phase and/or frequency difference between the first clock signal and the second clock signal. During test, the transmitter and the receiver can be directly or capacitively coupled to each another. Specifically, during test, the serial interface can be configured so that the transmitter transmits data using the first clock signal, and the receiver receives data using the second clock signal. The clock and data recovery functionality of the receiver can be tested by comparing the transmitted data with the received data.

Circuitry to facilitate testing of serial interfaces

Some embodiments provide a clock and data recovery (CDR) system to recover clock and data information from an analog signal. The CDR system may include an integral path and a proportional path that are part of an integral-proportional control loop. The integral path may be used to track frequency changes in a clock signal that is embedded in the analog signal, while the proportional path may be used to track phase changes in the clock signal that is embedded in the analog signal. The proportional path may be executed at a first clock frequency, while the integral path may be executed at a second clock frequency that is lower than the first clock frequency to reduce the power consumption of the CDR system.

Reducing power consumption in clock and data recovery systems

An integrated circuit that includes a receive data path is described. The receive data path: equalizes a received analog signal, converts the resulting equalized analog signal to digital data values based on a clock signal, and recovers the clock signal in the digital data values. The integrated circuit also includes an on-chip oscilloscope. The oscilloscope includes: two comparators, a phase rotator that outputs an oscilloscope clock signal whose phase can be varied relative to that of the recovered clock signal, and an offset circuit that outputs a voltage offset. Based on the voltage offset and the oscilloscope clock signal, the comparators output digital values which can be used to determine eye patterns that correspond to the analog signal before and after equalization. The eye patterns can then be correlated with an error rate associated with the received data.

Multiple-input, on-chip oscilloscope

A pulse response for a receiver, as an array PR, is found from the receiver's symbol stream. For a continuous stream of arbitrary data, a value of the array PR[k] can be determined from the signal levels of the symbols received. The stream of received data is input to a FIFO. Between the first and last locations of the FIFO is the symbol referred to herein as D. Symbols located in the FIFO before Dare referred to as D. Symbols located in the FIFO after Dare referred to as D. Ddiffers from the other FIFO symbols in that its signal level can be measured with an adjustable error slicer. The ISI effect of any Dupon Dcan be measured, and thus any PR[k] measured, by measuring the average signal level of Dwhen only certain types of data streams occur in the FIFO.

Method and apparatus for receiver pulse response determination

One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency fby varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f=f/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.

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Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each iteration, the system can use the receiver's clock and data recovery (CDR) circuitry to determine the number of early and late data transitions associated with one or more data patterns. Next, the system can adjust the one or more equalization parameters so that, for each data pattern in the one or more data patterns, the ratio between the number of early data transitions and the number of late data transitions is substantially equal to a desired value.

Method and apparatus for performing adaptive equalization

An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a recovered clock signal and a recovered bit-stream. The phase sweeping circuitry can receive the recovered clock signal, and output the scope clock signal by adding a phase offset to the recovered clock signal. A scope slicer can receive the voltage threshold, the scope clock signal, and the input signal, and output a scope bit-stream. The eye-diagram data collection circuitry can detect one or more bit-patterns in the recovered bit-stream, and modify values of one or more scope counters based solely or partly on the scope bit-stream and the recovered bit-stream.

Pattern agnostic on-die scope

Some embodiments of the present invention provide a voltage-mode transmitter. The transmitter can include configuration circuitry, bias circuitry, and a set of driver slices. Each driver slice can include driver transistors which drive an output value. The outputs of each driver slice can be directly or capacitively coupled with the transmitter's outputs. Each driver slice can also include one or more impedance-matching transistors which are serially coupled to at least some of the driver transistors. The configuration circuitry can configure a subset of driver slices so that the down (or up) impedance of the transmitter is within a first tolerance of a desired impedance value. The bias circuitry can bias the one or more impedance-matching transistors in each driver slice in the subset of driver slices so that the up (or down) impedance is within a second tolerance of the down (or up) impedance.

Circuitry for matching the up and down impedances of a voltage-mode transmitter

The DC offset of a differential signal can be changed by differentially shifting the DC offset of each of its signals. Techniques are presented for changing, in a controlled way, the DC offset of a differential signal as received by a receiver of a data transmission system. Several classes of example embodiments, utilizing digitally controllable voltage or current sources, are presented. The classes differ based upon such factors as coupling capacitor arrangement and use of termination resistors. Specific embodiments, within each class, differ based upon such factors as whether voltage or current sources are used and the characteristics of such sources. Once the DC offset of a differential signal has been changed, the effect of such change on a performance metric can be measured. Example applications include the ability to determine a differential signal level that results in BER having a particular level and determination of differential signal margin.

Method and apparatus for performance metric compatible control of data transmission signals

Some embodiments of the present invention provide a programmable transmitter which includes a set of drivers and one or more chains of configuration registers. Each driver is capable of being configured to perform a transmission function from a predetermined set of transmission functions. Each configuration register can correspond to a driver, and can store configuration data which is used to configure the corresponding driver. The programmable transmitter can include configuration circuitry which serially shifts configuration data into the one or more chains of configuration registers. The programmable transmitter can also include programming circuitry which can determine configuration data for each driver based partly or solely on a desired transmitter behavior.

Programmable transmitter

An eye opening measurement technique, that does not interrupt a receiver's normal operation, is used as a metric for optimizing any selected parameters of the receiver's operation. If eye opening size decreases, as a result of a change to a receiver parameter, the polarity for stepwise changes is reversed such that the next change is in the opposite direction. Other types of search procedures can be used. Eye opening size is the difference between the eye's upper and lower edges. Measurement of eye opening size is accomplished using a data and auxiliary slicer that find each 'edge' of an eye opening based upon the slicers' level of agreement. Depending upon the level of agreement, and whether symbols of the upper or lower region of the eye are counted, the threshold of the auxiliary slicer can be adjusted in the direction necessary to converge on the eye edge sought.

Method and apparatus for eye-opening based optimization

Probability distribution functions (PDFs), of a periodic input data signal, can be used to provide eye-diagram information. An advantage of PDFs, over conventional approaches to eye-diagram collection, is that analog-to-digital conversion can be accomplished by the slicer of a receiver, provided the slicer can programmably change its threshold. A cumulative distribution function (CDF), at a particular phase of a desired eye-diagram, can be collected by having a receiver's slicer scan its threshold level. For each threshold level, a fixed number of symbols can be analyzed as follows to produce a CDF value: count the number of times a particular symbol value occurs. The derivative of a CDF can produce its PDF, where each PDF can represent a 'slice' of a desired eye-diagram. For a non-periodic input signal, an eye diagram can still be formed so long as the percentage occurrence, of each symbol value, remains at least approximately the same.

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Allentown, PA, United States of America

Daniel Keith Weinlader