Sperry Corporation

Unisys Corporation

Daniel K Zenk

John R Trost

Wayne A Michaelson

A priority scheme is utilized wherein various Instruction Processors possess predetermined levels of prioritization for gaining storage access. Basically, access locking devices used in this environment perform the function of allowing a single port requester to gain unlimited access to the storage unit port while preventing or locking out access by all other requesters seeking access to that same port. In operation, a plurality of pending prioritized port requests are 'snapped' into a plurality of input latches. This snapping step is often referred to as a 'snapshot'. It is only during this 'snapshot' period that pending port requests are allowed to enter the priority latches. In past systems, when a port request was made, accompanied by an access lock signal, all port requests presently residing in the priority latches waiting to be serviced were cleared out and no new requests were accepted into the latches until the next 'snapshot' was performed. By causing these lower priority pending requests to be cleared out and not reinstated until a successive 'snapshot', many such pending requests timed-out. This invention reduces the number of pending requests timing out.

Access lock apparatus for use with a high performance storage unit of a

In an n-wide (n nominally equals 4) snapshot priority network apparatus the access of n+1 requestors to a memory unit is prioritized. Two requestors--the lowest priority one of normal system requestors called instruction processors plus a maintenance exerciser type requestor--share a single memory port which is nominally the lowest priority one of n such prioritized ports. Requests from both requestors are both honored upon a single priority snap, the instruction processor request nominally proceeding before the maintenance processor request. Although the n-wide priority network remains generally faster than any (n+1)-wide priority network, the maintenance exerciser type requestor is expediently serviced and cannot be locked out of access to memory by the competing higher priority requests of the instruction processor.

Modified snapshot priority enabling two requestors to share a single

A system for accelerating the granting of prioritized memory requests to a multi port memory system of a data processing system is disclosed. The priority requestor accelerator system detects the fact that one remaining requestor is in the priority memory system. The priority system logic is cleared out before the end of the normal requestor cycle. This allows the acceptance of a new set of requestors to be presented to the priority circuits at that time rather than waiting until presentation of the final request. Thus, the accelerator detects that the requestors from a previous requesting snap are on their last cycle. This allows a preclearance of the lower ranks as the priority circuit finishes its last cycle. The new requests are then loaded and the priority inputs are snapped shut beginning a new set of cycles. The overall operation happens as if the priority circuit is just moving from one requestor to another that is already in residence after the snap. Without this acceleration, a full memory cycle would have been lost with each reloading of the priority register.

Priority requestor accelerator

A maintenance exerciser makes requests of certain inoperative and malfunctioning storage memory bank portions of a large scale storage memory unit concurrently that normal system requestors do request of remaining, correctly functional, storage memory bank portions of such storage memory unit. All requests are collectively prioritized in a priority network which, save for the circuit of the present invention, will not advance to successive prioritizations until each currently prioritized request is positively acknowledged by the requested storage memory bank. When the maintenance exerciser makes abundant and repetitive requests to storage memory banks which are non-responding, resulting that such requests would time-out save for the circuit of the present invention, then such requests of the maintenance exerciser which would time-out would, by suspending successive prioritizations, significantly impede the concurrent access of normal system requestors to remaining correctly functional and responsive storage memory banks. A time delay circuit accomplishes a forced clear of an unacknowledged request from a maintenance exerciser to an unresponsive storage memory bank in the present invention, thereby simultaneously forceably precluding, or clearing, that the maintenance exerciser should experience a time-out to the requested memory while allowing the priority network to continue successive prioritizations.

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Stillwater, MN, United States of America

Daniel K Zenk