International Business Machines Corporation

Daniel Joseph Mainiero

William John Livingstone

David James Hathaway

Douglas Wayne Kemerer

Joseph Leonard Metz

Peter Anton Habitz

Paul Steven Zuchowski

Jeannie H Panner

Laura R Darden

James J Engel

Jeannie Therese Harrigan Panner

Michael Timothy Trick

Jeannie Therese Panner

An integrated circuit chip having at least one source pin and a plurality of sink pins. A wire segment connects the source pin to at least one of the sink pins and includes at least two segments where one of the segments is larger than the other where electromigration is likely to occur.

Semiconductor wiring technique for reducing electromigration

A computerized tool or method that calculates the capacitance and resistance of each global wire on the chip, one wire at a time. The invention steps along a track containing a wire segment, grid point by grid point, calculating the resistance and capacitance at that point. At each grid point it searches the neighboring tracks within the surrounding cube for adjacent elements that could cause capacitive effects or affect the resistance of the wire. The method delivers capacitance and resistance values for each process condition for a grid unit length of wire, given the wire type and 3 dimensional environment of the wire segment. The capacitance and resistance at a grid point along the wire are generally determined by one table lookup for wire types based on the surrounding environment. These values are added along wire segments to deliver accurate 3 dimensional capacitances and resistances. The invention can also provide for wires and spaces of various types and widths not provided for in the tables and for calculation of net to net coupling capacitances.

Three dimensional track-based parasitic extraction

A method for wiring IC chips such that electromigration criteria are met while minimizing the effect on overall chip wireability. A technique to optimize the width of automatically routed wire segments so that these widths are adequate to support the electromigration current on that net as a function of the capacitive loading of the net itself.

Wiring design tool improvement for avoiding electromigration by

Growing community of inventors

Williston, VT, United States of America

Daniel Joseph Mainiero