Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Daniel Joseph Linnen

Kirubakaran Periyannan

Ramanathan Muthiah

Avinash Rajagiri

Jayavel Pachamuthu

Ashish Ghai

Yehuda Hahn

Srikar Peesari

Alexander Bazarsky

Ariel Navon

Dongxiang Liao

Jagdish Sabde

Khanfer Kukkady

Shay Benisty

William Bernard Boyle

Niles Yang

Preston Allen Thomson

Ofir Pele

Shantanu Gupta

Everett Lyons, Iv

Randy Gillespie

Eran Sharon

Gautam Ashok Dusija

Mark Murin

Rohit Sehgal

Mark Shlick

Shrikar Bhagath

Tomer Tzvi Eliash

Philip David Reusswig

Abhijit K Rao

San A Phong

Cheng-Chung Chu

Rajan Paudel

Nika Yanuka

Sukhminder Singh Lobana

Narendhiran Cr

Gunter Knestele

Bin Wu

Nikita Thacker

Aashish Sangoi

Noor Mohamed Aa

Yuvaraj Krishnamoorthy

Bharath Radhakrishnan

Inez Hua

Elliott Peter Rill

Hoang Huynh

Muralitharan Jayaraman

Rampraveen Somasundaram

Sundar Panneer Selvam

James Tom

Durga Praveen Maddineni

Janet George

Prakash Subedi

Grant Chapman Mackey

Elliott Rill

Abhinav Anand

Ashish Pal Singh Ghai

Jay Dholakia

Dat Dinh

A process for reliably erasing data from a solid-state drive (SSD) includes first, prior to user data being stored on the drive, generating a restore image of information stored on the drive which characterizes a restore state of the drive, such as a factory image. Then, imparting energy to the drive to promote electrons representing bits in corresponding memory cells to exit the cells, such as imparting thermal energy or high-energy electromagnetic radiation to the drive. Also, generating a set of quantitative data for verifying erasure of the data for presentation to the user helps ensure trust in the data wipe process. The drive may also be electrically erased prior to imparting energy to the SSD, to provide another level of confidence in the data wipe process. The restore image may then be loaded to the necessary locations on the wiped drive to restore drive functionality.

Solid-state drive secure data wiping for reuse and recycling

Data storage devices configured to exploit generative-adversarial-networks (GANs). The GANs include super-resolution GANs (SRGANs). In some examples, a GAN-based reconstruction procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated.

Data storage device configured for use with a generative-adversarial-network (GAN)

Rather than storing multiple video files in a jumbo block (JB), the video file is stored in one or more complete JBs while the remaining data of the video file that does not fill a complete JB is stored in a tail block (TB). Generally, data sets are not mixed within a JB, but rather, the extra, excess, or tail data is stored in the TB. Multiple video file extra, excess, or tail data can be stored in a common TB. Stated another way, a TB is able to hold multiple video file tails from multiple video files. The use of the TB decreases garbage collection (GC) of jumbo blocks.

Avoiding garbage collection in media storage devices

Data storage devices configured to exploit generative-adversarial-networks (GANs). The GANs include super-resolution GANs (SRGANs). In some examples, a GAN-based decoding (reconstruction) procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure to permit a reduction in the number of parity bits used while storing the data. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated.

Recurrent Neural Networks (RNNs) wherein a non-volatile memory (NVM) array provides a memory bank for the RNN. The RNN may include a Neural Turning Machine (NTM) and the memory bank may be an NTM matrix stored in the NVM array. In some examples, a data storage device (DSD) that controls the NVM array includes both a data storage controller and a separate NTM controller. The separate NTM controller accesses the NTM matrix of the NVM array directly while bypassing flash translation layer (FTL) components of the data storage controller. Additionally, various majority wins error detection and correction procedures are described, as well as various disparity count-based procedures.

Memory (NVM) devices for use with recurrent neural networks

When copy commands are queued in a submission queue, there can potentially be many queued input-output (I/O) commands directed to the same logical range as the queued commands. This can result in data being invalidated immediately after it is written in memory, leading to write amplification and inefficient backend processing. To address this problem, the embodiments presented herein can be used to lock the range of logical block addresses of the queued commands, so that I/O commands are prevented from accessing the range of logical block addresses until the queued copy commands are completed.

Data storage device and method for logical range lock

For bit errors caused by intrinsic cell variations, the bit errors are scattered across a page of memory. However, for bit errors caused by a physical issue in memory, the bit errors cluster together within the same memory area. In an example data storage device, a page of memory is divided into sections, and counters are used to count the number of errors in each section. A physical error location is detected if the number exceeds a parameter, and as compared to the number of errors in the other sections. In another example data storage device having an error correction code (ECC) engine, a histogram and binomial probability are used to detect physical errors. This has the advantage of detecting weak memory blocks that are about to fail, so the blocks can be retired early as a grown bad block.

Data storage device and method for identifying a failing area of memory based on a cluster of bit errors

A data storage device can store data and parity information for the data in its memory. In some storage methodologies, data and parity information are striped across a plurality of memory dies (e.g., in a redundant array of independent drives (RAID) configuration). That way, if one of the memory dies fails, the data or the parity information can be reconstructed from the other memory dies. These embodiments recognize that because parity information is used relatively infrequently, the parity information can be stored in locations in the memory that have a relatively-worse performance than other areas of the memory. This can increase performance of the memory in situations where the parity information does not need to be read.

Data storage device and method for performance-dependent storage of parity information

Post-write data management operations, such as refresh read, data scrub, and data relocation, are typically performed after a certain period of time has elapsed. However, performing such operations based on probability of access can provide advantages. So, in one example, a post-write data management operation is performed more frequently on relatively-warmer data than on relatively-colder data.

Data storage device and method for time-pooled hot data relocation

The disclosure relates in some aspects to an apparatus that includes stages of a failure event counting circuit including an Nstage where N refers to an arbitrary stage of the stages of the failure event counting circuit. The Nstage may include an Nfuse trigger circuit configured to receive an event detector signal indicative of a failure event, an Nelectronic fuse configured to disconnect a circuit path between a voltage source and a ground in response to the event detector signal, and an Ndelay circuit coupled to the Ne-fuse and configured to cause a time delay for activating a subsequent stage of the failure event counting circuit in response to the Ne-fuse disconnecting. In this aspect, each of the stages of the failure event counting circuit may be configured to use the respective e-fuse to record a discrete failure event.

Multiple stage fuse circuitry for counting failure events

Methods and apparatus for efficiently handling large data files and their updates in NAND memory. In one example, provided is a data-storage system configured to reduce the frequency of data relocations by segregating a large data file into a plurality of subfiles. The size of such subfiles is appropriately selected to reduce the probability of occurrence for host-relocation conflicts and the magnitude of write amplification, thereby enabling the data-storage system to provide better quality of service while substantially maintaining acceptable levels of other pertinent performance characteristics. In some examples, a sequence of host read-modify-write commands is handled by generating a copy of implicated subfiles in a data buffer, applying subfile updates to the copy in the data buffer in accordance with the sequence, and relocating the implicated subfiles in the NAND memory using the updated versions thereof from the data buffer.

Segregating large data blocks for data storage system

Methods for recording commands in memory and providing the recorded commands. In one embodiment, a data storage controller includes a memory interface configured to interface with a memory, a controller memory including a storage firmware and a record mapping table, and a processor. The processor, when executing the storage firmware, is configured to receive a record identifier, receive a command including data to be stored in the memory, and create an entry in the record mapping table associating the record identifier with a logical block address of the command. The command is received after the record identifier. The processor may receive a playback identifier that includes the record identifier and determine, using the record mapping table, a location of the associated command in the memory. The command is provided to an external device.

Record and playback commands for storage devices

Data storage devices configured to exploit generative-adversarial-networks (GANs). The GANs include super-resolution GANs (SRGANS). In some examples, a GAN-based decoding reconstruction procedure is implemented within a data storage controller to replace or supplement an error correction coding (ECC) decoding procedure. In other examples, soft bit information is exploited using GANs during decoding. A dissimilarity matrix may be generated to represent differences between an initial image and a GAN-reconstructed image, with matrix values mapped into low-density parity check (LDPC) codewords to facilitate LDPC decoding of data. In still other examples, confidence information obtained from a GAN is incorporated into image pixels. In some examples, GAN reconstruction of data is limited to modifying valley bits. Multiple GANs may be used in parallel with their outcome aggregated.

Clamped semiconductor wafers and clamped semiconductor devices include reservoirs filled with a flowable metal which hardens to allow the wafers/devices to be shipped or stored. The hardened metal may also be reflowed to a liquid to allow clamping of the semiconductor wafers together and to allow clamping of the semiconductor packages together. The flowable metal may be filled into the reservoirs as a liquid or paste. Thereafter, the flowable metal may be cooled to harden the flowable metal into a clamping member.

Clamped semiconductor wafers and semiconductor devices

Bit-flip object insertion techniques are provided for use with a non-volatile memory (NVM) wherein an object is inserted into a background image by flipping or inverting one or more bits within the pixels of the background image that correspond to the shape and insertion location of an object being inserted. In an illustrative example, pixels within the background image that correspond to the shape and insertion location of the object are XORed with binary 1s. This flips the bits of those pixels to change the color (hue) and/or intensity (brightness) of the pixels so the object appears in the background image. In other examples, only the most significant bits of pixels in the background image are inverted (flipped). Exemplary latch-based procedures are described herein for high-speed processing on an NVM die. Multiple plane NVM die implementations are also described for massive processing.

Non-volatile memory die with bit-flip object insertion

Growing community of inventors

Naperville, IL, United States of America

Daniel Joseph Linnen