International Business Machines Corporation

Intermec IP Corporation

Ericsson Ab

Other

Globalfoundries Inc.

Intermac IP Corp.

Intermac Technologies Corporation

Intemec IP Corp.

Daniel Joseph Friedman

Jose A Tierno

Alexander V Rylyakov

Bodhisatwa Sadhu

Mark Ferriss

Alberto Valdes Garcia

Harley K Heinrich

Herschel Akiba Ainspan

Dharmendra S Modha

John Francis Bulzacchelli

Bipin Rajendran

Yong Liu

Woogeun Rhee

Leland Chang

Robert K Montoye

Jae-sun Seo

Bernard V Brezzo

Duixian Liu

Thomas Anthony Cofino

Chung H Lam

Seongwon Kim

Dah-Weih Duan

Kenneth Alan Goldman

Alberto Valdes-Garcia

Mounir Meghelli

Ghavam G Shahidi

Paul Andrew Moskowitz

John Vernon Arthur

Paul A Merolla

Steven Kyle Esser

Wooram Lee

Mihai A Sanduleanu

Sudipto Chakraborty

Frank Robert Libsch

Richard Harold Boivie

Scott Kevin Reynolds

Seiji Munetoh

Charanjit Singh Jutla

Kevin Patrick McAuliffe

Xiaoxiong Gu

Devendra K Sadana

Vijay Narayanan

Hayden C Cranford, Jr

Dirk Pfeiffer

Ramachandran Muralidhar

Eduard Albert Cartier

Robert L Wisnieff

Michael John Brady

Thomas Helmut Toifl

Danny Elad

Mark B Ritter

Kohji Hosokawa

Sergey Vladimirovich Rylov

Wanki Kim

Chandrasekara Kothandaraman

Paul William Coteus

Daniel Mark Dreps

Kerry Bernstein

Philip George Emma

Ruchir Puri

Albert M Young

Arun Sridhar Natarajan

David James Frank

Jeannine Madelyn Trewhella

Leonard Rexberg

Ibrahim M Elfadel

Han Chen

Mehmet Soyuer

Ankur Agrawal

Timothy O Dickson

Ofer Markish

Ola Ragnar Tageman

Peter George Capek

Arun Paidimarri

Christian Wilhelmus Baks

Lei Shan

Noam Kaminski

John Ulrich Knickerbocker

Rajiv V Joshi

Chandrasekhar Narayanaswami

Frank David Ferraiolo

Griselda Bonilla

Joseph Andrew Iadanza

Jean-Olivier Plouchart

Roman Vaculin

Chitra K Subramanian

Michael Sperling

Todd Morgan Rasmus

James Thomas Rayfield

Wing Kin Luk

Glen Arthur Wiedemeier

Dale L Scott

Monty Montague Denneau

Carrie Ellen Cox

Trieu Can Chieu

Andrew Douglas Davies

Ismael Faro Sertage

Sudhir Muniswamy Gowda

Ralph Linsker

Matthew Beck

A base substrate, high-k substrate layers on the base substrate with discrete decoupling capacitors embedded, high density substrate layers on the high-k substrate layers supporting wiring and wiring spacing of less than 2 up to about 10 micron width, pitch connectivity between the upper surface of the base substrate and a lower surface of the set of high density substrate layers supports less than 50 up to about 300 micron pitch, the pitch connectivity on an upper surface of the set of high density substrate layers supports less than about 150 micron pitch. A method including attaching a set of metal posts at each contact on a lower surface of a set of high density substrate layers, attaching to a handler, attaching an interconnect layer to a base substrate, and attaching the set of high density substrate layers to the base substrate while aligning each metal post with a contact.

Electronic substrate stacking

A current mode end-to-end signal path includes, a digital to analog converter (DAC), operating in current mode and an upconverting mixer, operating in current mode and operatively coupled to the DAC, wherein analog inputs and analog outputs of the DAC and the upconverting mixer are represented as currents, and the DAC generates a baseband signal.

Current mode signal path of an integrated radio frequency pulse generator

A variable capacitor device comprises first and second control paths which are configured to enable differential control using first and second transistors of a same doping type in the first and second control paths, respectively, wherein the first and second transistors are configured as voltage variable resistors for tuning a capacitance of the variable capacitor device.

Variable capacitor devices with differential voltage control

A device comprises a voltage-mode filter circuit, a current-mode output circuit, and a regulation circuit. The voltage-mode filter circuit is configured to generate a voltage signal on an output terminal thereof. The current-mode output circuit comprises an input transistor which comprises a gate terminal coupled to the output terminal of the voltage-mode filter circuit, and a source terminal coupled to a regulated node. The regulation circuit is configured to adjust a voltage level on the regulated node to maintain a constant gate-source bias voltage for the input transistor to generate a current for biasing the current-mode output circuit.

Low voltage signal path in a radio frequency signal generator

Techniques are provided for calibrating signal currents in a radio frequency signal generator system, such as an arbitrary waveform generator system. A device comprises a current measurement circuit and a current imbalance correction circuit. The current measurement circuit is configured, during a calibration process, to measure a first current in a first signal path of a radio frequency signal generator, and to measure a second current in a second signal path of the radio frequency signal generator. The current imbalance correction circuit is configured to adjust a current level in at least one of the first signal path and the second signal path of the radio frequency signal generator to correct for an imbalance between the measured first current and the measured second current.

Calibrating signal currents in a radio frequency signal generator

Antenna package structures are provided to implement wireless communications packages. For example, an antenna package includes multilayer package substrate, a planar antenna array, antenna feed lines, and resistive transmission lines. The planar antenna array includes an array of active antenna elements and dummy antenna elements surrounding the array of active antenna elements. Each active antenna element is coupled to a corresponding one of the antenna feed lines, and each dummy antenna element is coupled to a corresponding one of the resistive transmission lines. Each resistive transmission line extends through the multilayer package substrate and is terminated in a same metallization layer of the multilayer package substrate.

Wireless communications package with integrated antenna array

A method (and structure) includes receiving a challenge for an authentication, in a chip having stored in a memory device therein a secret to be used in an authentication attempt of the chip by an external agent. The chip includes a hardware processing circuit to sequentially perform a processing related to the secret. The secret is retrieved from the memory device and processed in the hardware processing circuit in accordance with information included in the received challenge. The result of the processing in the hardware processing circuit is transmitted as a response to the challenge. The hardware processing circuit executes in a parallel manner, thereby reducing a signal that can be detected by an adversary attempting a side channel attack to secure the secret.

Cryptographic side channel resistance using permutation networks

An example operation may include one or more of receiving, via a network, tag data that is read from a tag associated with a physical object and signed with a key assigned to the tag, determining, via a blockchain peer, that the signed tag data is validly signed based on a corresponding key pair of the tag which is accessible to the blockchain peer, determining, via the blockchain peer, whether the tag data satisfies of one or more predefined conditions of the physical object, and storing the determination via a blockchain database.

Storage and communication environment for cryptographic tags

A single flux quantum (SFQ) circuit includes a radio frequency (RF) to direct current (DC) conversion stage. A DC to RF current conversion stage is coupled to a single output of the RF to DC conversion stage. The DC to RF current conversion stage includes a plurality of series stacked Josephson Junctions (JJs) having n stages, configured to convert a DC current received from the RF to DC conversion stage and reconvert the DC current to an RF tone.

Josephson RF to RF frequency converter

Embodiments of the invention relate to a time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network. One embodiment comprises maintaining neuron attributes for multiple neurons and maintaining incoming firing events for different time steps. For each time step, incoming firing events for said time step are integrated in a time-division multiplexing manner. Incoming firing events are integrated based on the neuron attributes maintained. For each time step, the neuron attributes maintained are updated in parallel based on the integrated incoming firing events for said time step.

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network

One embodiment relates to a neuromorphic network including electronic neurons and an interconnect circuit for interconnecting the neurons. The interconnect circuit includes synaptic devices for interconnecting the neurons via axon paths, dendrite paths and membrane paths. Each synaptic device includes a variable state resistor and a transistor device with a gate terminal, a source terminal and a drain terminal, wherein the drain terminal is connected in series with a first terminal of the variable state resistor. The source terminal of the transistor device is connected to an axon path, the gate terminal of the transistor device is connected to a membrane path and a second terminal of the variable state resistor is connected to a dendrite path, such that each synaptic device is coupled between a first axon path and a first dendrite path, and between a first membrane path and said first dendrite path.

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.

Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology

Devices, computer-implemented methods, and systems that can facilitate radio frequency identification components are provided. According to an embodiment, a device can comprise a memory that can be coupled to an integrated circuit device that can have a processor and an accelerator component that can execute a cryptographic module. The device can further comprise a radio frequency identification device that can be coupled to the integrated circuit device that can communicate with a radio frequency identification reader device based on the cryptographic module.

Radio frequency identification based integrated computer with hardware accelerator

Embodiments provide for a portable imager by capturing several radar readings related to an object in an environment over several times from several of Points of View (POV), wherein each radar reading indicates a distance to and reflectivity of the object relative to the imager; capturing several camera images of the environment over the several of times from the several POVs; determining positional shifts of the imager over the several times based on photogrammetrical differences between subsequent camera images of the several camera images; determining, based on accelerometer data, a trajectory that the imager moves in the environment over the several times; determining positions of the imager in the environment over the several times based on the positional shifts and the trajectory; combining the several radar readings based on the positions to produce a synthetic aperture radar image of the object; and outputting the synthetic aperture radar image.

Portable imager

Growing community of inventors

Sleepy Hollow, NY, United States of America

Daniel Joseph Friedman