Hewlett-packard Development Company, L.P.

Daniel Joseph Dove

Mark Gravel

Joseph A Curcio

Keng Hua Chuang

Yee Hong Tan

Lawrence Lee Chee How

Joseph A Curclo, Jr

Kenneth Boyd Neal

Systems, methods, and devices are provided for a multiplexed serial media independent interface (--N,). One system for handling data includes a physical layer (PHY) circuit (--N,--N) operating at a first rate including a number of ports (--P), a media access control (MAC) circuit (--N) operating at the first rate including a number of ports, and a multiplexed serial media independent interface (--N,) between the MAC circuit (--N) and the PHY circuit (--N,--N) operating at a second rate, which is greater than the first rate. The interface (--N,) includes a number of conductors and is configured to communicate data between the MAC circuit (--N) and the PHY circuit (--N,--N) via four conductors per up to eight ports (--P) of the PHY circuit (--N,--N).

Multiplexed serial media independent interface

A system for power distribution to network devices in a powered network is described herein. The system includes a first power sourcing equipment (PSE) device, which is configured to communicate data and selectively provide power to one or more devices. The system further includes a second PSE device coupled to the first PSE device through a network cable. The second PSE device is configured to communicate data, selectively provide power to one or more devices, and to receive a probing input through the network cable. The second PSE device includes a false detection mitigation circuit, which is configured to increase a leakage current of the second PSE device. The increased leakage current is associated with a resistive signature that is outside of a resistive range of a valid powered device.

Increasing leakage current of power source unit to adjust input resistance at network port for mitigating false detection as powered device

Unshielded twisted pair (UTP) termination circuits, UTP termination circuit systems, and methods of terminating an UTP circuit are provided. UTP termination circuits can include a plurality of resistors in parallel, where each of the plurality of resistors is configured to be coupled to one of a plurality of unshielded twisted pairs of an UTP cable, a shunt resistor is coupled in series with the plurality of parallel resistors, and a capacitor is connected to ground in series with the shunt resistor.

Unshielded twisted pair termination circuit

An electronic device includes an illuminable indicator, a presence detector, and a controller. The illuminable indicator is to indicate information to a user of the electronic device by one or more of being illuminated and not being illuminated. The presence detector is to detect presence of the user in proximity to the electronic device regardless of whether the user is moving or is stationary. Absence of the user is inferred upon the presence detector not detecting the presence of the user. The controller is to enable the illuminable indicator based at least on the presence of the user as detected by the presence detector and to disable the illuminable indictor based at least on the absence of the user. Enablement of the illuminable indicator does not mean that the illuminable indicator is necessarily illuminated. Disablement of the illuminable indicator means that the illuminable indicator is never illuminated while disabled.

Illuminable indicator of electronic device being enabled based at least on user presence

A physical layer device includes a pseudo-random number generator, a register, a state machine, and a timer. The pseudo-random value generator is configured to produce a pseudo-random value within a predefined range. The register is configured to receive the pseudo-random value from the pseudo-random value generator and store the pseudo-random value. The state machine is configured to obtain the pseudo-random value from the register and provide the pseudo-random value to a timer within the physical layer device. The timer is configured to control a duration of an Energy Efficient Ethernet time period based on the pseudo-random value.

Energy efficient ethernet control

One embodiment disclosed relates to a system for power distribution to network devices. The system includes a plurality of network switches each having an internal power supply and a plurality of ports for connecting to the network devices and an external power supply having a plurality of output ports for connecting to the network switches. The external power supply communicates power available to the network switches. Each network switch determines amounts and priority levels of power for the network devices connected thereto, sums together the amounts at each priority level, determines additional amounts and priority levels of power required beyond the internal power supply capability, and sends a power request to the external power supply. The external power supply allocates power to the network switches depending on the power requests received.

Method and system for distributing power to networked devices

A variable depth buffer includes: a set of buffer units to receive input data in a First in First Out (FIFO) manner, with links between the buffer units such that the input data can be transferred sequentially from a first buffer unit that initially receives the input data to each subsequent buffer unit in the set; and a multiplexer, inputs of the multiplexer being connected to outputs of the respective buffer units and an output of the multiplexer to output data such that a depth of the buffer varies depending on which buffer unit output is selected by the multiplexer.

Variable depth buffer

A method performed by a networked device for energy efficient operation of an optical transceiver of the networked device is described herein. It is determined whether a port control of the networked device is enabled to operate in an energy efficient state. Where the port control is enabled to operate in the energy efficient state and an absence of a valid receive energy from a link partner is determined, a laser transmitter of the optical transceiver is pulsed by asserting and de-asserting a control signal.

Method for energy efficient pulsing operation of transceivers of a networked device

A plurality of media access controllers (MACs) are time division multiplexed with one or more serializer/deserializer (SerDes) devices, wherein there are more MACs than SerDes devices and/or a single multi-rate Ethernet MAC is able to communicate with a multi-rate PHY spanning speeds from 10 megabits per second to 10 gigabits per second using the same framing mechanism and structure.

Highly flexible and efficient MAC to PHY interface

A system for controlling power supplied by a power supply comprises an attachment device and a circuit coupled to the supply and operable to be coupled to the attachment device, the circuit operable to determine if the attachment device has an authorized source, the circuit further operable to disable power supplied to the attachment device if the attachment device does not have the authorized source.

System for controlling current flow to electronic attachment device

In an embodiment of the invention, a method for negotiating link speed and configuration, includes: performing a modulation of a data D with contents of a synchronous scrambler in order to generate a modulated output Z, where the data D includes configuration information; transmitting the modulated output across a link; and demodulating the modulated output Z with the contents of a synchronous descrambler in order to recover the data D.

Method and apparatus for negotiating link speed and configuration

A Gigabit Media Independent Interface (RGMII), which is adapted to also implement a ten bit interface (RTBI) that is intended to be an alternative to both the IEEE 802.3z GMII and the TBI is disclosed. The interface has a reduced number of input and output pins, i.e., pin-count, that can implement the above GMII and TBI standards. More particularly, the interface reduces the number of pins required to interconnect the MAC and the PHY from a maximum of 28 pins (TBI) to 13 pins in a cost effective and technology independent manner. The RGMII maps pins to transfer data at the same data rate with control functionality with a minimum number of input and output pins, and does so by utilizing both the rising and falling edges of the clock signal and complies with existing interface specifications set forth in the IEEE standards.

Reduced pin-count system interface for gigabit ethernet physical layer devices

A method of automatically configuring media connections when operating in forced speed and duplex mode, includes: connecting a first pair of connectors to a first pair of conductors and a second pair of connectors to a second pair of conductors during a first state, and connecting the first pair of connectors to the second pair of conductors and the second pair of connectors to the first pair of conductors during a second state; and holding the first state or the second state if operating in forced speed and duplex mode, a defined time has not expired and another end of a link can receive a signal. An apparatus for automatically configuring media connections when operating in forced speed and duplex mode, includes: a media switch.

Growing community of inventors

Colfax, CA, United States of America

Daniel Joseph Dove