Graphcore Limited

Microsoft Technology Licensing, LLC

Xmos Limited

Graphcore Limtied

Daniel John Pelham Wilkinson

Stephen Felix

Richard Luke Southwell Osborne

Alan Graham Alexander

Simon Christian Knowles

David Lacey

Graham Bernard Cunningham

Brian Manula

Matthew David Fyles

Jonathan Mangnall

Stavros Volos

Ola Tørudbakken

Harald Høeg

Richard William Osborne

Balaji Vembu

Bjorn Dag Johnsen

Kapil Vaswani

Cédric Alain Marie Fournet

Samuel Alexander Webster

Manuel Costa

Ola Torudbakken

David Thomas Chisnall

Saurabh Mohan Kulkarni

Martin G Vickers

Ian James Quinn

Michael David May

Lars Paul Huse

Hachem Yassine

Andrew Stanford-Jason

Harald Hoeg

Kenneth Gordon

Nigel Jürgen Toon

Owain Jones

Ola TØRUNDBAKKEN

Harald HØEG

A peripheral device, for use with a host, comprises one or more compute elements a security module and at least one encryption unit. The security module is configured to form a trusted execution environment on the peripheral device for processing sensitive data using sensitive code. The sensitive data and sensitive code are provided by a trusted computing entity which is in communication with the host computing device. The at least one encryption unit is configured to encrypt and decrypt data transferred between the trusted execution environment and the trusted computing entity via the host computing device. The security module is configured to compute and send an attestation to the trusted computing entity to attest that the sensitive code is in the trusted execution environment.

Peripheral device

A processing system comprising one or more chips, each comprising a plurality of tiles is described. Each tile comprises a respective processing unit and memory, the memory storing a codelet. The processing system has at least one encryption unit configured to encrypt and decrypt data transferred between the tiles and a trusted computing entity via an external computing device. The codelets are configured to instruct the tiles to transfer the encrypted data by reading from and writing to a plurality of memory regions at the external memory such that a plurality of streams of encrypted data are formed, each stream using an individual one of the memory regions at the external computing device.

Streaming data to multi-tile processing system

The same test data frame is dispatched from a network interface device a plurality of times so as to test a network. Since the same test data frame is used, it may be unnecessary for a new test data frame to be provided and protocol processed each time one is required to be sent. The protocol processing resources of the network interface device are then available for sending further traffic in parallel with the dispatch of the test data frames. On the receive side, the network interface device collects statistics regarding the reliable receipt of test frames, without requiring the test frames to be further processed and provided to a driver of the network interface device. In this way, the processing and buffering capacity in the network interface device is available for handling further traffic in parallel with the test traffic.

Network path testing via independent test traffic

A memory attachment and routing chip includes a single die having a set of external ports; at least one memory attachment interface comprising a memory controller to attach to external memory, and a fabric core in which routing logic is implemented. The routing logic can (i) receive a first packet of a first type from a first port of the set of ports, the first type of packet being a memory access packet with a memory address which lies in a range of memory addresses associated with the memory attachment and routing chip, detect the memory address and route the packet of the first type to the memory attachment interface. The routing logic can (ii) receive a second packet of a second type, the second type of packet being an inter-processor packet comprising a destination identifier identifying a processing chip external to the memory attachment.

Computer system having a chip configured for memory attachment and routing

Each of the nodes stores a number, referred to herein as a generation number, which is updated whenever the respective node undergoes a reset and restart from checkpoint. Since the nodes of the system participate in the same reset event, at most times, each generation number held by a node will be the same across the system. However, in some cases, when one node resets before another node, the generation numbers between those two nodes will differ. The data frames sent between the nodes each comprise a generation number of the sending node, which is checked by the recipient and only accepted if the generation number in the frames matches the generation number of the recipient node.

Reset of a multi-node system

A new apparatus and method for securely distributing an application to processors of a processing unit. The processing unit is formed as part of an integrated circuit and comprises a plurality of processors (referred to as tiles), each having their own execution unit and storage for storing application data and additional executable instructions. The integrated circuit comprises a hardware module (referred to herein as the autoloader) that is configured to distribute a set of bootloader instructions (referred to herein as a secondary bootloader) to each of at least some of the tiles. Each of the tiles then executes instructions of the received secondary bootloader, which causes each tile to issue read requests to read a set of executable application instructions from a memory external to the integrated circuit. Each tile then performs operations using the received set of executable application instructions so as execute the application using the processing unit.

Hardware autoloader

A gateway for interfacing a host with a subsystem for acting as a work accelerator to the host. The gateway enables the transfer of batches of data to the subsystem at precompiled data exchange synchronisation points. The gateway acts to route data between accelerators which are connected in a scaled system of multiple gateways and accelerators using a global address space set up at compile time of an application to run on the computer system.

Gateway fabric ports

The invention relates to a computer program comprising a sequence of instructions for execution on a processing unit having instruction storage for holding the computer program, an execution unit for executing the computer program and data storage for holding data, the computer program comprising one or more computer executable instruction which, when executed, implements: a send function which causes a data packet destined for a recipient processing unit to be transmitted on a set of connection wires connected to the processing unit, the data packet having no destination identifier but being transmitted at a predetermined transmit time; and a switch control function which causes the processing unit to control switching circuitry to connect a set of connection wires of the processing unit to a switching fabric to receive a data packet at a predetermined receive time.

Instruction set

A system and method for encrypting and decrypting data exchanged between a multi-tile processing unit and a storage, where a plurality of keys are used for the encryption. Each of the plurality of keys is associated with a different one or more sets of the processors. Encryption hardware is configured to select a key to use for encryption/decryption operations in dependence upon the set of tiles associated with the data being exchanged. Each write request from a tile contains identifier bits associated with that tile's set of tiles, enabling the encryption hardware to select the key to use for encrypting the data in the write request. Each read completion for a tile contains identifier bits associated with that tile's set of tiles, enabling the encryption hardware to select the key to use for decrypting the data in the read completion.

Multiple key management

Each of the processing devices stores an event vector, which is updated when certain events (e.g. memory errors, overtemperature events) occur on the device. Different elements of the vector correspond to different types of events. When an event of a given type occurs on one device, the update to the event vector on that device is propagated to other devices in the system. Those other devices, in response, update the corresponding element in their own event vector to indicate that an event of that given type has occurred in the system. In this way, events are aggregated between the different devices using the event vector. The event vector is considered to be a global event vector, since its elements indicate whether certain events have occurred across the entire system, and the vector is consistent across the system.

Global event aggregation

A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that processing unit.

Synchronisation for a multi-tile processing unit

A device comprising: a processing unit comprising at least one processor configured to: participate in barrier synchronisations, each of which separates a compute phase of the at least one processor from an exchange phase for the at least one processor; and exchange sync messages with a sync controller hardware unit so as to co-ordinate each of the barrier synchronisations; and sync trace circuitry configured to: receive one or more of the sync messages; and in response to each of the one or more of the sync messages, provide sync trace information for output from the device, the sync trace information comprising timing information associated with the respective sync message.

Tracing synchronization activity of a processing unit

A predictive clock controller is provided for modifying the frequency of a clock signal provided to a processing unit based on knowledge of the power usage by the application running on the processing unit during different execution periods. The predictive clock controller counts barrier syncs for the application, so as to determine where the application is in its sync schedule. The predictive clock controller is able to determine from the number of counted syncs, when the application will transition from one execution period to another execution period with different power requirements, and to adjust the clock frequency accordingly.

Predictive clock control

A system comprising: a first subsystem comprising at least one first processor, and a second subsystem comprising one or more second processors. A first program is arranged to run on the at least one first processor, the first program being configured to send data from the first subsystem to the second subsystem. A second program is arranged to run on the one more second processors, the second program being configured to operate on the data content from the first subsystem. The first program is configured to set a checkpoint at one or more points in time. At each checkpoint it records in memory of the first subsystem i) a program state of the second program, comprising a state of one or more registers on each of the second processors at the time of the checkpoint, and ii) a copy of the data content sent to the second subsystem since the respective checkpoint.

Growing community of inventors

West Harptree, United Kingdom

Daniel John Pelham Wilkinson