Wolfspeed, Inc.

Cree Fayetteville, Inc.

Daniel John Martin

Brice McPherson

Alexander B Lostetter

Jennifer Stabach

Matthew Feurtado

Ty McNutt

Blake Whitmore Nelson

Austin Curbow

Brian DeBoi

Brett Edward Sparkman

Paul Wheeler

William Austin Curbow

The present disclosure relates to a power module with a power path extending through a first field-effect transistor (FET) and a second FET. A primary conductive structure connecting the first FET and the second FET in series provides a primary parasitic inductor within the power path. A first secondary conductive structure connected to both a gate and a source of the first FET provides a first secondary parasitic inductor within a first gate path, and a second secondary conductive structure connected to both a gate and a source of the second FET provides a second secondary parasitic inductor within a second gate path. The first secondary conductive structure and the second secondary conductive structure are configured such that mutual coupling between the first secondary parasitic inductor and the primary parasitic inductor and mutual coupling between the second secondary parasitic inductor and the primary parasitic inductor are substantially symmetrical.

Optimization of power module performance via parasitic mutual coupling

The disclosure is directed to a power module that includes at least one power substrate, a housing arranged on the at least one power substrate, and a first terminal electrically connected to the at least one power substrate. The first terminal includes a contact surface located above the housing at a first elevation. The power module includes a second terminal including a contact surface located above the housing at a second elevation different from the first elevation, a third terminal electrically connected to the at least one power substrate, and a plurality of power devices electrically connected to the at least one power substrate.

High power multilayer module having low inductance and fast switching for paralleling power devices

A power module includes a power substrate, a number of power semiconductor die, and a number of connector pins. The power substrate includes a number of conductive traces. The power semiconductor die are mounted on the power substrate and electrically coupled to the conductive traces. The connector pins are each electrically coupled to a different one of the conductive traces and configured to be interconnected such that the power semiconductor die provide an active front-end and a switching power converter. By providing the power semiconductor die such that they can be interconnected to form an active front-end and a switching power converter in the same power module, the power module may provide a significantly more compact power converter system using both an active front-end and switching power converter.

Integrated power module

A package for power electronics includes a power substrate, a number of power semiconductor die, and a Kelvin connection contact. Each one of the power semiconductor die are on the power substrate and include a first power switching pad, a second power switching pad, a control pad, a semiconductor structure, and a Kelvin connection pad. The semiconductor structure is between the first power switching pad, the second power switching pad, and the control pad, and is configured such that a resistance of a power switching path between the first power switching pad and the second power switching pad is based on a control signal provided at the control pad. The Kelvin connection pad is coupled to the power switching path. The Kelvin connection contact is coupled to the Kelvin connection pad of each one of the power semiconductor die via a Kelvin conductive trace on the power substrate.

Package for power electronics

A device binning and/or matching process includes measuring with a testing device currents and/or voltages of a device with respect to time, determining with the testing device binning and/or matching criteria for the device based on transfer data generated from the device currents and/or the voltages measured with respect to time, and outputting with the testing device the binning and/or matching criteria for the device. A system and power module are also disclosed.

Methods and systems for matching both dynamic and static parameters in dies, discretes, and/or modules, and methods and systems based on the same

A power module including at least one substrate, a housing arranged on the at least one power substrate, a first terminal electrically connected to the at least one power substrate, a second terminal including a contact surface, a third terminal electrically connected to the at least one power substrate, a plurality of power devices arranged on and connected to the at least one power substrate, and the third terminal being electrically connected to at least one of the plurality of power devices. The power module further including a base plate and a plurality of pin fins arranged on the base plate and the plurality of pin fins configured to provide direct cooling for the power module.

The disclosure is directed to a power module apparatus that includes a base plate, a power substrate positioned relative to the base plate, at least two power contacts, a gate-source board mounted relative to the power substrate, gate drive connectors electrically connected to the gate-source board, a housing secured to the power substrate, and a clamping circuit electrically connected to the at least one power device. The clamping circuit being configured to clamp an input to a gate of the at least one power device. The clamping circuit being arranged with at least one of the following: the base plate, the power substrate, one of the at least two power contacts, the at least one power device, the gate-source board, the gate drive connectors, and the housing. The disclosure is further directed to a process of configuring a power module apparatus.

Power modules having an integrated clamp circuit and process thereof

A power module apparatus includes a power substrate, at least one power device electrically connected to the power substrate and a gate-source board mounted relative to the power substrate, the gate-source board electrically connected to the at least one power device, a housing secured to the power substrate, and a clamping circuit electrically connected to the at least one power device. The clamping circuit being configured to reduce a voltage charge up at a gate of the at least one power device to within 8 V of a desired voltage.

Growing community of inventors

Fayetteville, AR, United States of America

Daniel John Martin