Apple Inc.

Okta, Inc.

Proxy, Inc.

Motiv, Inc.

Daniel Jeffrey Post

Nir Jacob Wakrat

Vadim Khmelnitsky

Matthew John Byom

Kenneth Louis Herman

Andrew W Vogan

Anthony Fai

Tahoma Madrone Toelkes

Hsiao Thio

Eric Brandon Tamura

Alexander C Sanks

Michael Jurgen Strasser

Curt C Von Badinski

Barry J Corlett

Peter Miles Twiss

Eric Strasser

Brian Sutton

Anthony Ambuehl

Dominic Benjamin Giampaolo

David Michael Chan

Conrad Sauerwald

Neil Gareth Crane

Erik C Neuenschwander

Ken Herman

Puja Dilip Gupta

Sam Sanjabi

Daniel E Crosby

Benjamin H Nham

Francois Barbou-des-Place

Naomaru Itoi

Royal Chan

Vincent Voong

Hari Hara Kumar Maharaj

An identity provider ('IdP') system maintains a framework of authentication methods and security targets that enables flexible authentication policy authoring and analysis of authentication performed by users of an organization. The IdP system generates authentication method profiles that include authentication factors and attributes, which may be further classified as required or optional. The IdP system also generates security target profiles that indicate security requirements needed to satisfy the corresponding security targets. The IdP system uses the generated profiles to determine relationships between authentication methods and security targets (e.g., a list of authentication methods that satisfy a given security target). Using these relationships, the IdP system may enable users to author policies and analyze how users' authentication behaviors comply with security targets.

Security guidance for creation of multi factor authentication policy

The disclosure discloses a wearable computing device (WCD) that would selectively and automatically activate a transceiver of the WCD for data transmission based on sensor data obtained from a sensor module of the \VCD. In some example, the sensor module may convert the physical movements of the WCD into sensor data. Then, a processor module of the WCD compares the sensor data to a predetermined pattern pre-stored in the memory. If the sensor data matches the predetermined pattern, the processor module activates the transceiver to receive/transmit data packets. If the sensor data does not match the predetermined pattern, the process goes back to the beginning, where the processor module monitors the movement of the WCD through the sensors.

Wearable device and data transmission method

The disclosure discloses a wearable computing device (WCD) that would selectively and automatically activate a transceiver of the WCD for data transmission based on sensor data obtained from a sensor module of the WCD. In some example, the sensor module may convert the physical movements of the WCD into sensor data. Then, a processor module of the WCD compares the sensor data to a predetermined pattern pre-stored in the memory. If the sensor data matches the predetermined pattern, the processor module activates the transceiver to receive/transmit data packets. If the sensor data does not match the predetermined pattern, the process goes back to the beginning, where the processor module monitors the movement of the WCD through the sensors.

Systems and methods are disclosed for efficient buffering for a system having non-volatile memory ('NVM'). In some embodiments, a control circuitry of a system can use heuristics to determine whether to perform buffering of one or more write commands received from a file system. In other embodiments, the control circuitry can minimize read energy and buffering overhead by efficiently re-ordering write commands in a queue along page-aligned boundaries of a buffer. In further embodiments, the control circuitry can optimally combine write commands from a buffer with write commands from a queue. After combining the commands, the control circuitry can dispatch the commands in a single transaction.

Efficient buffering for a system having non-volatile memory

Systems and methods are disclosed for configuring a non-volatile memory ('NVM'). In some embodiments, each block of the NVM can include a block table-of-contents ('TOC'), which can be encoded (e.g., run-length encoded) and dynamically-sized. Thus, as user data is being programmed to a block, the size of a block TOC can be concurrently recalculated and increased only if necessary. In some embodiments, the NVM interface can use a weave sequence stored in the context information and at least one weave sequence associated with each page of a block to determine whether to replay across the pages of the block after system boot-up.

Systems and methods for configuring non-volatile memory

Systems and methods are provided for unmapping unused logical addresses at mount-time of a file system. An electronic device, which includes a non-volatile memory ('NVM'), may implement a file system that, at mount-time of the NVM, identifies all of the logical addresses associated with the NVM that are unallocated. The file system may then pass this information on to a NVM manager, such as in one or more unmap requests. This can ensure that the NVM manager does not maintain data associated with a logical address that is no longer needed by the file system.

Mount-time unmapping of unused logical addresses in non-volatile memory systems

Systems and methods are disclosed for generating efficient reads for a system having non-volatile memory ('NVM'). A read command can be separated by a host processor of the system into two phases: a) transmitting a command to a storage processor of the system, where the command is associated with one or more logical addresses, and b) generating data transfer information. The host processor can generate the data transfer information while the storage processor is processing the command from the host processor. Once the data transfer information has been generated and data has been read from the NVM, the data can be transferred.

Generating efficient reads for a system having non-volatile memory

Systems and methods are disclosed for logical block address ('LBA) bitmap usage for a system having non-volatile memory ('NVM'). A bitmap can be stored in volatile memory of the system, where the bitmap can store the mapping statuses of one or more logical addresses. By using the bitmap, the system can determine the mapping status of a LBA without having to access the NVM. In addition, the system can update the mapping status of a LBA with minimal NVM accesses. By reducing the number of NVM accesses, the system can avoid triggering a garbage collection process, which can improve overall system performance.

LBA bitmap usage

Systems and methods are disclosed for providing a weave sequence counter ('WSC') for non-volatile memory ('NVM') systems. The WSC can identify the sequence in which each page of the NVM is programmed. The &#x201c;weave&#x201d; aspect can refer to the fact that multiple blocks can be open for programming at once, thus allowing the pages of these blocks to be programmed in a &#x201c;woven&#x201d; manner. Systems and methods are also disclosed for providing a host weave sequence counter (&#x201c;HWSC&#x201d;). Each time new data is initially programmed to the NVM, this data can be associated with a particular HWSC. The HWSC associated with the data may not change, even when the data is moved to a new page (e.g., for wear leveling purposes and the like). The WSC and HWSC may aid in, for example, performing rollback, building logical-to-physical mappings, determining static-versus-dynamic page statuses, and performing maintenance operations (e.g., wear leveling).

Weave sequence counter for non-volatile memory systems

Systems and methods are disclosed for correcting block errors. In particular, a system can store a parity page per page-modulo, where a pre-determined number of pages of a block or a band of the NVM may be allocated as page-modulo XOR ('PMX') parity pages. This enables a space efficient approach for recovering from single-block data errors.

Correction of block errors for a system having non-volatile memory

Systems and methods are provided for storing data to or reading data from a non-volatile memory ('NVM'), such as flash memory, using a metadata redundancy scheme. In some embodiments, an electronic device, which includes an NVM, may also include a memory interface for controlling access to the NVM. The memory interface may receive requests to write user data to the NVM. The user data from each request may be associated with metadata, such as a logical address, flags, or other data. In response to a write request, the NVM interface may store the user data and its associated metadata in a first memory location (e.g., page), and may store a redundant copy of the metadata in a second memory location. This way, even if the first memory location becomes inaccessible, the memory interface can still recover the metadata from the backup copy stored in the second memory location.

Metadata redundancy schemes for non-volatile memories

This can relate to non-regular parity distribution of a non-volatile memory ('NVM'), such as flash memory, and detection of the non-regular parity via a metadata tag. For example, each codeword of the NVM can include one or more parity pages that may be distributed at random through the NVM. To identify the page as a parity page, a parity page marker can be included in the metadata of that page. During power-up of the NVM, an address table including the logical-to-physical address mapping of the pages can be created. Pages including a parity page marker, however, can be skipped during the creation of this address table. Additionally, by having two or more parity pages associated with a codeword, an additional layer of protection can be provided for repairing errors in that codeword.

Non-regular parity distribution detection via metadata tag

Systems and methods are disclosed for stochastic block allocation for improved wear leveling for a system having non-volatile memory ('NVM'). The system can probabilistically allocate a block or super block for wear leveling based on statistics associated with the block or super block. In some embodiments, the system can select a set of blocks or super blocks based on a pre-determined threshold of a number of cycles (e.g., erase cycles and/or write cycles). The block or super block can then be selected from the set of super blocks. In other embodiments, the system can use a fully stochastic approach by selecting a block or super block based on a biased random variable. The biased random variable may be generated based in part on the number of cycles associated with each block or super block of the NVM.

Growing community of inventors

Campbell, CA, United States of America

Daniel Jeffrey Post