International Business Machines Corporation

Daniel James Sucher

Raymond E Losinger

Fabrice Jean Verplanken

Jean Louis Calvignac

Daniel Frank Moertl

Bruce Marshall Walk

Patrick Kevin Egan

Glen Howard Handlogten

James Francis Mikos

Jeffrey James Lynch

David Alan Norgaard

Thomas James Osten

William John Goetzinger

Joseph P Buonomo

Burton L Oliver

John J Erhard

David L Livingston

A scheduler for a network processor includes one or more scheduling queues. Each scheduling queue defines a respective sequence in which flows are to be serviced. A respective empty indicator is associated with each scheduling queue to indicate whether the respective scheduling queue is empty. By referring to the empty indicators, it is possible to avoid wasting operating cycles of the scheduler on searching scheduling queues that are empty.

Empty indicators for weighted fair queues

A 2-bit communication channel is made to transmit complex data patterns by partitioning a digital string into 3-bit binary patterns which are encoded into 4 bits binary pattern and transmitted over the 2-bit communication channel in pairs using adjacent clock cycles on the 2-bit channel. Pre-defined ones of the 4-bit encoded data structures are used for framing on the channel and cannot be used to transmit data.

Method and apparatus for transmission on a 2-bit channel using 3b/4b code

An enhanced peripheral component interconnect (PCI) architecture for a data-processing system is described. In accordance with the method and system of the present invention, a peripheral component interconnect (PCI) architecture for a data-processing system comprises a PCI host bus, a number of PCI local buses, and a PCI hot-plug bridge. Each of the local PCI buses has an adapter card slot. The PCI hot-plug bridge, connected between the PCI host bus and the PCI local buses, is utilized for controlling power to each of the PCI local buses, such that a PCI adapter card may be removed from or added to any one of the adapter card slots during power up while there is processing ongoing within adapter card(s) situated in other adapter card slot(s).

Peripheral component interconnect (PCI) architecture having hot-plugging

A computer system has a universal channel and control unit to interface, with a minimum complexity, to a plurality of different I/O adapters such as a Token Ring adapter or an Ethernet adapter. The system comprises a main processor with main memory, an I/O processor coupled to the main processor by a bus, and a channel program which runs on the I/O processor. The channel program accesses the processor and main memory. The channel program and main processor communicate with a first I/O program protocol. A control unit program also runs on the I/O processor and interfaces the channel program to a plurality of different I/O adapters with a second relatively simple, universal I/O program protocol. Each of the I/O adapters also has a different I/O program protocol than the other I/O adapters and the first I/O protocol, for communication with their respective device.

Channel and control unit having a first I/O program protocol for

The performance of a multi-microprocessor implemented data processing system that emulates a mainframe system is enhanced and optimized in view of space and power constraints for purposes of address translation by providing RAM-based storage means of predetermined depth and width to function as a page address table. The storage means depth is set to at least provide bit space to represent the total number of fixed size pages possible in a given virtual memory space. The width of the storage means is set to at least provide bit space to represent the largest page number that might be encountered in the available real memory and to accommodate a predetermined number of bits that flag information pertinent to translation and system performance. Circuit means, including microcode, is provided for initializing and updating the contents of the storage means as required. Further, when the translation capability is off, a real out-of-bounds flag bit in the storage means can be used to dynamically insure that a real out-of-bounds condition is not produced. The storage means is coupled to the microprocessor address bus from when it receives the page portion of a virtual address for which a real address is desired.

Apparatus and method for effecting dynamic address translation in a

Synchronization of peripheral operation with that of a processor in a multi-microprocessor implemented data processing system is achieved by bus cycle alteration. A logic circuit is provided for monitoring the condition of a peripheral's status bits and for preventing an appropriate processor control signal from completing the present bus cycle if the peripheral of interest is not able to accept an access. The peripheral of interest is readily identified by providing unique memory mapped locations, one for each system peripheral, that are responsively connected to the logic circuit.

Apparatus and method for synchronization of peripheral devices via bus

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Rochester, MN, United States of America

Daniel James Sucher