Lsi Corporation

Lsi Logic Corporation

Daniel James Murray

Jonathan W Byrn

Gary Scott Delp

Paul Gary Reuland

Robert Neal Carlton Broberg, Iii

Troy Evan Faber

A method and apparatus for floor-plan region creation and placement is provided. Design information may be received. Module area may be estimated for each module in an integrated circuit. Individual module may be selected for regioning, and region size and dimensions for module may be determined. Region parameters may be adjusted prior to final placement and placement may be verified.

Method and apparatus for automatic creation and placement of a floor-plan region

A method and apparatus are provided for identifying a potential floorplan problem in an integrated circuit layout pattern. The method and apparatus identify a critical timing path in the layout pattern and identify a start point and one or more end points along the timing path. It is then determined whether any of the one or more end points are floor-planned objects. For each end point that is a floor-planned object, the method and apparatus compare a distance between that end point and the start point with a distance threshold to produce a comparison result. A potential floorplan problem can be identified if the distance exceeds the distance threshold.

Method of identifying floorplan problems in an integrated circuit layout

A register address generation tool is used during the design of semiconductor products. For those registers and/or memories that are addressable on a bus, the register address generation tool creates the interconnect RTL, header files, static timing analysis constraint files, and verification testcases. The tool also maintains coherence between what has been generated and the available resources for the design of the semiconductor product in a design. If there are any registers and/or memories that are not being used, the register address generation tool may further generate the RTL that will convert these unused resources to performance-enhancing features such as control registers, status registers, etc. The register address generation tool read a design database having an application set to determine what hardmacs and what transistor fabric is available. It also receives as input a bus specification and address parameters. The register address generation tool may be used with a suite of generation tools to achieve the rapid design and realization of a new semiconductor product.

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Rochester, MN, United States of America

Daniel James Murray