Linear Technology Corporation

Daniel James Eddleman

Zhizhong Hou

Mitchell Edward Lee

Christopher Bruce Umminger

Chad Thomas Steward

In one embodiment, a pass MOSFET is coupled in series between an input voltage and a load, and a bypass capacitor is connected in parallel with the load. In response to a voltage step across the MOSFET, the MOSFET is adaptively controlled to conduct an in-rush current of 2I=2Iduring the bypass capacitorcharging time, where Iis the capacitive current and Iis the load current. This optimizes the in-rush current to achieve a minimum peak temperature of the MOSFET. In one embodiment, a ramp capacitor connected to the drain of the MOSFET is part of a feedback path that tracks the MOSFET drain voltage to control the gate voltage.

Adaptive in-rush current control for minimizing MOSFET peak temperature upon voltage step

A circuit for protecting a semiconductor element is provided in a system for supplying power from an input node to an output node. The circuit has an analog multiplier responsive to a voltage across the semiconductor element and a current flowing through the semiconductor element to produce an output voltage. A transconductance amplifier is coupled to an output of the analog multiplier for receiving the output voltage of the analog multiplier to produce an output current. An analog RC circuit coupled to the output of the transconductance amplifier is configurable to include a selected number of resistive elements having selected resistance values and a selected number of capacitive elements having selected capacitance values. The configuration of the RC circuit is carried out to provide an RC thermal model that reproduces a desired thermal behavior of the semiconductor element. The RC circuit is responsive to the output current of the transconductance amplifier to produce an output voltage used to control the semiconductor element.

MOSFET protection using resistor-capacitor thermal network

A novel readdressing circuit is provided for supporting data communications over a data line and a clock line between at least one master device and multiple slave devices. For example, the master device and the multiple slave devices may be configured to communicate over an I2C bus including the data line and the clock line. The readdressing circuit has a data input node for receiving a data signal transferred over the data line and including an address word produced by the master device, and a data output node coupled to the multiple slave devices. The readdressing circuit also includes an address generator and an address transmit detections circuit. The address generator is configured for storing a multi-bit fixed offset value. The address generator is responsive to the address word at the data input node for generating multiple unique addresses for the multiple slave devices. The address transmit detection circuit is configured for enabling the address generator to generate the multiple unique addresses at the data output node when the address word is detected at the data input node, and for preventing an output signal of the address generator from being supplied to the data output node when no address word is detected at the data input node.

Address translation in I2C data communications system

A converter may generate an analog output that is representative of a time-encoded signal. The circuit may include an input port receiving the time-encoded signal; a time-encoded to digital converter coupled to the input port; and a digital-to-analog converter coupled to the time-encoded to digital converter.

Converting time-encoded signal into analog output

The present invention relates to methods and circuits for controlling outputs of one or more slave power supplies in one or more defined relationships to a master signal. The defined relationships include but are not limited to coincident tracking, offset tracking, ratiometric tracking, and supply sequencing.

Methods and circuits for tracking and sequencing multiple power supplies

The present invention comprises methods and circuits for mirroring input current in multiple stages to improve the accuracy of the mirrored output current over a wide dynamic range of input current. The current mirror circuit of the present invention automatically (1) detects an increasing magnitude of input current and (2) adapts the current mirror circuit to accommodate the increasing magnitude.

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San Jose, CA, United States of America

Daniel James Eddleman