International Business Machines Corporation

Globalfoundries Inc.

Daniel Jacob Fainstein

Norman Whitelaw Robson

Toshiaki Kirihata

Chandrasekharan Kothandaraman

Sami Rosenblatt

Subramanian Srikanteswara Iyer

John Matthew Safran

Yunsheng Song

Gary William Maier

Alberto Cestero

Methods and circuits for undiscoverable physical chip identification are disclosed. Embodiments of the present invention provide an intrinsic bit element that comprises two transistors. The two transistors form a pair in which one transistor has a wide variability in threshold voltage and the other transistor has a narrow variability in threshold voltage. The wide variability is achieved by making a transistor with a smaller width and length than the other transistor in the pair. The variation of the threshold voltage of the wide variability transistor means that in the case of copies of intrinsic bit elements being made, some of the 'copied' wide variability transistors will have significantly different threshold voltages, causing some of the intrinsic bit elements of a copied chip to read differently than in the original chip from which they were copied.

Undiscoverable physical chip identification

Embodiments of the present invention provide a chip authentication system using multi-domain intrinsic identifiers. Multiple intrinsic identifiers taken from multiple domains (areas or sections of the chip) are compared against the intrinsic identifiers collected during the manufacture of the chip. If at least one intrinsic identifier matches those collected during manufacture, the chip may be designated as authentic.

Chip authentication using multi-domain intrinsic identifiers

A method and system for testing one or more semiconductor structures, for example, chips or wafers, in a three-dimensional stack. The method and system includes controlling a logic signal of a first circuit in a first chip or wafer connected to a supply voltage to indicate a first state during pre-assembly testing of the first chip or wafer. The method and system further includes controlling the logic signal to indicate a second state when the first circuit is connected to a second circuit of a second chip or wafer resulting in a combined circuit. The combined circuit is in a three-dimensional chip or wafer stack during post-assembly testing of the three-dimensional chip or wafer stack.

Circuits for self-reconfiguration or intrinsic functional changes of chips before vs. after stacking

One of the wafers in a semiconductor wafer to wafer stack can be rotated a predefined number of positions, relative to a previous wafer in the stack, and bonded in the position in which the maximum number of good die are aligned. An adjustment circuit on each die reroutes signals received from a pad that has been relocated due to rotation. A communication channel formed from a pair of pads that are interconnected by a Through Substrate Vias can be placed in each die and can convey selected information from one die to the next. A code representative of the position orientation of each die can be recorded in a Programmable Read Only Memory located on each die, or may be down loaded from a remote source. Any additional wafer may be stacked serially, and each one may be rotated relative to the wafer that precedes it in the stack.

Physical design symmetry and integrated circuits enabling three dimentional (3D) yield optimization for wafer to wafer stacking

A random intrinsic chip ID generation employs a retention fail signature. A 1and 2ID are generated using testing settings with a 1setting more restrictive than the 2, creating more fails in the 1ID bit string that includes 2ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1ID includes the 2ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3ID with intermediate condition such that 1ID includes 3ID bit string and 3ID includes 2ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

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Beacon, NY, United States of America

Daniel Jacob Fainstein