Intel Corporation

Daniel J Zierath

Harsono S Simka

Sadasivan Shankar

Jason A Farmer

James S Clarke

Valery M Dubin

Christopher J Jezewski

Florian Gstrein

Tejaswi K Indukuri

Michael L McSwiney

Daniel B Bergstrom

Vinay B Chikarmane

Michael G Haverty

Chi-Hwa Tsang

Flavio Griggio

Shaestagir Chowdhury

Akm Shaestagir Chowdhury

John D Brooks

Radek P Chalupa

Iouri Lantassov

Terry T Buckley

Anand Durairajan

Provided herein are metal structures that may include a cobalt alloy, a nickel alloy, or nickel, as well as related devices and methods. The metal structures may be formed by chemical vapor deposition (CVD), and may include trace amounts of precursor materials used during the CVD process.

Metal structures, devices, and methods

Disclosed herein are integrated circuit (IC) interconnects, as well as related devices and methods. For example, in some embodiments, an interconnect may include a first material and a second material distributed in the first material. A concentration of the second material may be greater proximate to the top surface than proximate to the bottom surface.

Integrated circuit interconnects

In an example, there is disclosed a chemical compound, including a transition metal, a post-transition metal, a metalloid, and a nonmetal. By way of non-limiting example, the post-transition metal may be aluminum. The transition metal is selected from the group consisting of tungsten, tantalum, hafnium, molybdenum, niobium, zirconium, vanadium, and titanium. The metalloid may be boron or silicon. The nonmetal may be carbon or nitrogen. The compound may be used, for example, as a barrier material in an integrated circuit.

Diffusion barriers

A metal interconnect comprising cobalt and method of forming a metal interconnect comprising cobalt are described. In an embodiment, a metal interconnect comprising cobalt includes a dielectric layer disposed on a substrate, an opening formed in the dielectric layer such that the substrate is exposed. The embodiment further includes a seed layer disposed over the substrate and a fill material comprising cobalt formed within the opening and on a surface of the seed layer.

Cobalt based interconnects and methods of fabrication thereof

Techniques are disclosed that enable interconnects, vias, metal gates, and other conductive features that can be formed through electroless material deposition techniques. In some embodiments, the techniques employ electroless fill in conjunction with high growth rate selectivity between an electroless nucleation material (ENM) and electroless suppression material (ESM) to generate bottom-up or otherwise desired fill pattern of such features. Suitable ENM may be present in the underlying or otherwise existing structure, or may be provided. The ESM is provisioned so as to prevent or otherwise inhibit nucleation at the ESM covered areas of the feature, which in turn prevents or otherwise slows down the rate of electroless growth on those areas. As such, the electroless growth rate on the ENM sites is higher than the electroless growth rate on the ESM sites.

Electroless filled conductive structures

Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.

Liner layers for metal interconnects

An embodiment of the invention provides a method for reducing within die thickness variations by modifying the concentration of components of a low-acid electroplating solution. For one embodiment, the leveler concentration is increased sufficiently to reduce within die thickness variations to a specified value. For one embodiment of the invention, the leveler and suppressor are increased to reduce within die thickness variations and substantially reduce a plurality of electroplating defects. In such an embodiment the combined concentration of leveler and suppressor is determined to maintain adequate gap fill.

Modified electroplating solution components in a low-acid electrolyte solution

A method for an electroplating cell which includes providing an anode chamber with at least two concentric anodes including an inner anode and an outer anode; generating a computer generated model with a simulation computer program; and selecting at least one current ratio from the computer generated model, with the computer generated model having a plurality of current ratios from which the at least one current ratio is selected and the one current ratio being a ratio of an inner electrical current to an outer electrical current. The method further includes applying the inner electrical current to the inner anode and the outer electrical current to the outer anode and adjusting the inner and outer electrical currents to incorporate the one current ratio. The generating of the computer generated model with the simulation computer program includes using a first iterative loop to determine a potential field in the anode chamber.

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Portland, OR, United States of America

Daniel J Zierath