Xilinx, Inc.

Daniel J Rothman

David Chiang

Secure password organizer

An improved arithmetic logic unit (ALU) of an erasable-programmable logic device (EPLD) with a flexible, programmable carry function allows a broad range of functions to be implemented. The inventive circuit utilizes a separately configurable carry chain with multiple logic and arithmetic function capabilities.

Carry chain circuit with flexible carry function for implementing

The present invention allows initializing operations such as loading configuration data and preloading registers to begin before a user has released a reset signal. A circuit is provided which responds to the leading edge of a user's reset signal to generate an internal reset signal which begins the initializing operation. The circuit simultaneously starts a delayed signal which ends the internal reset signal. If the MRX signal is long, the chip becomes ready for operating upon release of the MRX signal, whereas if the MRX signal is short, the chip becomes ready for operating upon completion of any steps necessary for resetting the chip. In either case, after a reset signal is received, the chip becomes ready for operation in a shorter time than with the prior art circuits.

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Sunnyvale, CA, United States of America

Daniel J Rothman