International Business Machines Corporation

Globalfoundries Inc.

Daniel J Poindexter

Devendra K Sadana

Stephen W Bedell

Joel Pereira De Souza

James Douglas Warnock

Gregory Gower Freeman

Karen A Nummy

Stephan Alan Cohen

Siyuranga O Koswatta

J Campbell Scott

Gregory John Uhlmann

Leon Jacob Sigal

Paul Stephen McLaughlin

Keith C Stevens

James M Crafts

John W Lewis

Kenneth A Lavallee

Scott Taylor

Robert B McClure

George F Cunningham, Jr

Karre M Greene

A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided between an nsilicon layer and an oxide layer of an SOI substrate. The presence of the silicon buffer layer reduces electron injection into the oxide layer during device processing which requires an electric field.

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A sensor for on-chip monitoring the effects of operating conditions on a circuit, Integrated Circuit (IC) chips including the sensors, and a method of monitoring operating condition effects on-chip circuits, e.g., for the occurrence of electromigration. The sensor includes a multi-fingered driver associated with a monitored circuit, sensitive to known circuit parameter sensitivities. Sense and control logic circuit selectively driving the multi-fingered driver, and selectively monitoring for an expected multi-fingered driver response.

On-chip sensor for monitoring active circuits on integrated circuit (IC) chips

An efficient method of calculating maximum current limits for library gates in which a current limit includes the impact of self-heating effects associated with the maximum current. A maximum current solution is obtained in a self-consistent fashion, providing a way of determining the self-consistent solution in a rapid fashion without extensive numerical calculations or simulations. The present method provides a practical approach for characterizing a large library of gates for use in CMOS designs.

Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specifications

System and method using low voltage current measurements to measure voltage network currents in an integrated circuit (IC). In one aspect, a low voltage current leakage test is applied voltage networks for the IC or microchip via one or more IC chip connectors. One or multiple specifications are developed based on chip's circuit delay wherein a chip is aborted or sorted into a lesser reliability sort depending whether the chip fails specification. Alternately, a low voltage current leakage test begins an integrated circuit test flow. Then there is run a high voltage stress, and a second low voltage current leakage test is thereafter added. Then, there is compared the second low voltage test to the first low V test, and if the measured current is less on second test, this is indicative of a defect present which may result in either a scrap or downgrade reliability of chip.

Low-voltage IC test for defect screening

An improved reactive ion plasma etching apparatus having an improved electrode, for holding the product, such as a semiconductor wafer, to be etched, provided with a plurality of apertures into which different tailored product holders are inserted so as to alter the plasma over each holder and provide more uniform etching of the product in the holder regardless of its position on the electrode.

RF Coupling techniques

Growing community of inventors

Cornwall-on-Hudson, NY, United States of America

Daniel J Poindexter