International Business Machines Corporation

Infineon Technologies North America Corp.

Daniel J Nickel

John Edward Barth, Jr

William Paul Hovis

Howard L Kalter

Scott C Lewis

Charles E Drake

James A Yankosky

William F DeCamp

Steven H Voldman

Lars W Liebmann

John Atkinson Fifield

Mark Alan Lavin

John Kenneth DeBrosse

Richard Quimby Williams

William C Leipold

Scott Josef Bukofsky

Gordon A Kelley, Jr

Joseph J Oler, Jr

Cheryl A Hoffman

Roy S Bass, Jr

James Robert Montstream

Charles H Stapper

Juergen Preuninger

Daniel C Sullivan

Laurice Thorsen Earl

Marco Hug

Jason Steven Minahan

Kathleen McGroddy

A phase shift mask shape that reduces line-end shortening at the critical feature without changing layout size increases required of requisite phase shift rules. The phase feature is given an angled extension, which includes the lithographic shortening value. This allows the critical shape to be designed much closer to the reference layer then it could without the angled extension feature. Phase mask extension features beyond a given device segment are significantly reduced by lengthening the feature along an uncritical portion; moving the feature reference point to the device layer; and flattening the phase extension feature into an L-shape or T-shape along the uncritical parts of a device segment. Applying these design rules allows a draw of the gate conductor under current conditions and puts phase shapes inside without extending the gate conductor dimensions to the next feature.

Layout impact reduction with angled phase shapes

A system, method and program product for performing density checking of an IC design. The invention establishes an evaluation array for the IC design including an array element for each evaluation window of the IC design. The number of evaluation windows is based on a smallest necessary granularity. A single pass through shape data for the IC design is then conducted to populate each array element with a shape area for a corresponding evaluation window. Density checking is performed by iterating over the evaluation array using a sub-array. The sub-array may have the size of the preferred density design rule window. The invention removes the need for repetitive calculations, and results in a more efficient approach to density checking.

IC design density checking method, system and program product

A integrated circuit (IC) chip with ESD protection level and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design and array pads are wired to I/O cells located on the chip. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection level. The design is then verified by first identifying the chip pads, I/O cells and ESD protect devices. Connections between these three structures are verified. Wires between the ESD protect devices and the chip pads and I/O cells are shrunk such that unsuitable connections becomes opens (disconnected) and are found in subsequent checking. Finally connections to guard rings are checked. Power rails are checked in a similar manner.

Method of automated ESD protection level verification

A method using a generate-and-verify computer program product to generate by repetitive passes a design rules checking computer program, wherein the design rules are described in a file called a runset. The design rules checking program is used for exhaustive testing of VLSI chips for compliance to the design rules of a given VLSI fabrication process. The runset is repeatedly iterated in loop fashion with respect to a testcase file containing groups of layout structures or shapes used for verifying the correctness of the runset. A general purpose shapes processing program creates an error shapes file for storing geometrical errors found in each said layout structure. Two additional shapes are used in the verification process: user boundary shapes for defining areas in which errors are not to be detected for a given design rule, and automated boundary shapes created to surround each said layout structure with a boundary that defines regions where error shapes can occur. An association table is created which is a compilation of the error shapes, user boundary shapes, and automated boundary shapes associated with each layout structure. The association table is processed to determine the correctness of the runset. The runset is modified to correct each valid error. The repetitive passes continue until a final runset is generated. This final runset becomes the input to design rules checking computer program product and customizes the program for a given VLSI fabrication process.

Method for verifying design rule checking software

The techniques of the present invention facilitate the control of an IC chip fabrication level of a fabrication process based upon the design pattern of the IC chip being fabricated. A grid having multiple sections is imposed over the design pattern of a fabrication level of the IC chip. Then, pattern density values are automatically established for the design pattern contained in each section of the grid. The IC chip fabrication level is then controlled based upon the pattern density values. For example, the established pattern density values facilitate the automatic determination of a CMP process stop parameter, or the automatic compensation for etch rate variations caused by pattern density differences across the design pattern of the IC chip.

Method and system using the design pattern of IC chips in the processing

A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block provides both the corrected data bits and the check bits to an SRAM. Thus, the check bits can be externally accessed. At the same time, having a set of interrelated bits in the SRAM compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

Dynamic RAM with on-chip ECC and optimized bit and word redundancy

Low power addressing systems are provided which include a given number of memory segments, each having word and bit/sense lines, a given number of decoders coupled to the given number of memory segments for selecting one word line in each of the memory segments, a first plurality of transmission gate systems, each having first and second transmission gates, with each of the gates being coupled to a different one of the decoders, a second decoder having the first plurality of outputs, each of the outputs being coupled to a respective one of the transmission gate systems, first control circuits for selectively activating the first and second gates in each of the first plurality of transmission gate systems, a second given number of decoders coupled to the given number of memory segments for selecting one bit/sense line in each of the memory segments, a second plurality of transmission gate systems, each having first and second transmission gates, with each of the gates of the second plurality of transmission gate systems being coupled to a different one of the second given number of decoders, and second control circuits for selectively activating the first and second gates of each of the second plurality of transmission gate systems.

Low power addressing systems

Growing community of inventors

Westford, VT, United States of America

Daniel J Nickel