Mindspeed Technologies, Inc.

Maker Communications, Inc.

Conexant Systems, Inc.

Stratus Technologies Bermuda Ltd.

Daniel J Lussier

Joseph B Tompkins

Paul V Bergantino

Wilson Parkhurst Snyder, Ii

Simon P Graham

Duane E Galbi

Wilson P Snyder Ii

Steven Michael Haid

Jeffrey S Somers

John W Edwards, Jr

Bruce Burns

Timothy Wegner

A transparent high-availability solution utilizing virtualization technology is presented. A cluster environment and management thereof is implemented through an automated installation and setup procedure resulting in a cluster acting as a single system. The cluster is setup in an isolated virtual machine on each of a number of physical nodes of the system. Customer applications are run within separate application virtual machines on one physical node at a time and are run independently and unaware of their configuration as part of a high-availability cluster. Upon detection of a failure, traffic is rerouted through a redundant node and the application virtual machines are migrated from the failing node to another node using live migration techniques.

Systems and methods of high availability cluster environment failover protection

A system is provided for rapidly synchronizing two or more processing elements in a fault-tolerant computing system. Embodiments of this system allow for the rapid synchronization of two processing elements through partial copies of the contents of memory associate with each processing element.

Systems and methods for maintaining lock step operation

An integrated circuit for processing communication packets having separate data buffers and separate state information buffers. Each data buffer and each state information buffer (hereinafter termed resources) has an associated in-use counter. Multiple events can share the same resource. The counter associated with a resource is incremented when a resource becomes associated with a particular event. The counter associated with a resource is decremented when an event completes the use of that particular resource. When the in-use counter for a resource becomes zero, the in-use counter indicates that the resource is unassigned and that the resource can be assigned to a new event.

Method for automatic resource reservation and communication that facilitates using multiple processing events for a single processing task

An integrated circuit processes communication packets and comprises a pointer cache and control logic. The pointer cache store pointers that correspond to external buffers that are external to the integrated circuit and configured to store the communication packets. The control logic allocates the external buffers as the corresponding pointers are read from the pointer cache and de-allocates the external buffers as the corresponding pointers are written back to the pointer cache.

Integrated circuit that processes communication packets with a buffer management engine having a pointer cache

An integrated circuit processes a communication packet and comprises a core processor and scheduling circuitry. The core processor executes a software application that directs the core processor to process the communication packet. The scheduling circuitry retrieves first scheduling parameters cached in a context buffer for the packet and executes a first algorithm based on the first scheduling parameters to schedule subsequent transmission of the communication packet.

Integrated circuit that processes communication packets with scheduler circuitry that executes scheduling algorithms based on cached scheduling parameters

Circuitry to free the core processor from performing the explicit read operation required to read data into the internal register set. The processor's register set is expanded and a &ldquo;shadow register&rdquo; set is provided. While the core processor is processing one event the &ldquo;context&rdquo; and &ldquo;data&rdquo; and other associated information for the next event is loaded into the shadow register set. When the core processor finishes processing an event, the core processor switches to the shadow register set and it can begin processing the next event immediately. With short service routines, there might not be time to fully pre-fetch the &ldquo;context&rdquo; and &ldquo;data&rdquo; associated with the next event before the current event ends. In this case, the core processor still starts processing the next event and the pre-fetch continues during the event processing. If the core processor accesses a register which is associated with part of the context for which the pre-fetch is still in progress the core processor will automatically stall or delay until the pre-fetch has completed reading the appropriate data.

Enhancing performance by pre-fetching and caching data directly in a communication processor's register set

An integrated circuit comprises co-processor circuitry and a core processor. The co-processor circuitry comprises context buffers and data buffers. The co-processor circuitry receives and stores one of the communication packets in one of the data buffers. The co-processor circuitry correlates the one communication packet with one of a plurality of channel descriptors. The co-processor circuitry associates the one data buffer with one of the context buffers holding the one channel descriptor to maintain the correlation between the one communication packet and the one channel descriptor. The co-processor circuitry prevents multiple valid copies of the one channel descriptor from existing in the context buffers. In some examples of the invention, this is accomplished by tracking a number of the data buffers associated with the one context buffer. The core processor executes a packet processing software application that directs the processor to process the one communication packet in the one data buffer based on the one channel descriptor in the one context buffer.

Integrated circuit that processes communication packets with co-processor circuitry to correlate a packet stream with context information

An integrated circuit processes communication packets and comprises a core processor and scheduling circuitry. The core processor executes a software application that directs the core processor to process the communication packets. The scheduling circuitry comprises multiple scheduling boards where at least some of the scheduling boards have multiple priority levels. The scheduling circuitry processes the scheduling boards to schedule and subsequently initiate transmission of the communication packets.

Integrated circuit that processes communication packets with scheduler circuitry having multiple priority levels

An integrated circuit processes communication packets and comprises co-processor circuitry and a core processor. The co-processor circuitry is configured to operate in parallel with the core processor. The co-processor circuitry receives and stores the communication packets in data buffers. The co-processor circuitry also determines a prioritized processing order. The core processor executes a packet processing software application that directs the processor to process the communication packets in the data buffers based on the prioritized processing order.

Integrated circuit that processes communication packets with co-processor circuitry to determine a prioritized processing order for a core processor

Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. A group of bits comprises a primary scoreboard indicative of the scheduling status for cell time slots in a periodic container of cells, with each bit indicating the availability of a corresponding cell time slot. A connection identifier (ID) table is maintained with each location in the table corresponding to one of the cell time slots and thus a single primary scoreboard bit. A cell scheduling instruction specifies a connection ID for a virtual connection on an ATM transmission link. A processor searches the primary scoreboard until a bit corresponding to an available cell time slot is located, reserves the located cell slot by setting the corresponding bit, and stores the connection ID in the corresponding location in the connection ID table. A cell servicing instruction specifies an address in the connection ID table. The processor receives the servicing instruction, retrieves the corresponding primary scoreboard bit, constructs or retrieves a cell for transmission in the slot if the bit was set, and then clears the bit so the slot is available for subsequent scheduling requests. A secondary scoreboard may be used to bound the primary scoreboard search time. The secondary scoreboard includes a bit for each block of primary scoreboard bits. The bit indicates whether the primary scoreboard block includes an available time slot. Portions of the primary scoreboard with no available slots thus need not be searched. Separate tunnel control primary scoreboards may be used in conjunction with a master primary scoreboard to support virtual path tunneling.

Asynchronous transfer mode cell processing system with scoreboard scheduling

Asynchronous transfer mode cell processing system with scoreboard

Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor provides a cell buffer RAM (CBR) memory space gathering protocol which allows unused portions of a number of cell buffers to be addressed as a contiguous virtual memory space. The space gathering protocol may utilize a CPU or direct memory access (DMA) controller in an ATM cell processor to set a gather bit appended to a virtual CBR address. An address generator in the CBR detects the gather bit and translates those virtual addresses which include a set gather bit to physical addresses into the CBR memory space. The translation is performed by setting certain bits of the physical address to predetermined states to reach the unused 8 bytes at the bottom of any given 64-byte cell buffer, and shifting certain bits of the virtual address to other positions in the physical address to move from cell buffer to cell buffer in the contiguous virtual space. Multiple gather spaces may be supported in alternative embodiments by using a different number of gather bits.

Asynchronous transfer mode cell processing system with cell buffer space

Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor provides a modulo arithmetic feature which permits branching on the modulo portion of the result of an arithmetic operation. An arithmetic logic unit (ALU) or other processor instruction is modified to include a modulo field which specifies the number of right to left bits after which the result of the corresponding ALU operation will be truncated. Conditional branch instructions such as branch on zero result, branch on non-zero result, branch on negative result, branch on carry and branch on overflow may be configured to operate only on the modulo portion of the ALU instruction result and/or on a carry out of the most significant bit (MSB) position of the modulo portion.

Method and device for performing modulo-based arithmetic operations in

Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor includes a load multiple instruction which provides a burst transfer of a data block from an external control memory, and allows the result of a subsequent operation on a loaded value to be automatically written back to the control memory location from which it was previously read. The instruction may specify the address in the control memory of a data block to be retrieved, a destination register in a CPU register file into which the first retrieved halfword of a data block will be loaded, and a total number of halfwords to be retrieved. The instruction includes a link field option which directs the storage of information linking the processor registers which receive the retrieved halfwords to the control memory locations from which the halfwords were read. An automatic memory update feature may be provided in an arithmetic logic unit (ALU) instruction which operates on one or more of the processor registers receiving the halfwords retrieved by the instruction, such that the result of the corresponding ALU operation will be automatically written back to the control memory location or locations which supplied one or more of the operands.

Asynchronous transfer mode cell processing system with load multiple

Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor implements a 'bubble' count technique which efficiently accommodates multiple layers of scheduling requests and/or external cell sources. In the case of multiple layers of scheduling requests, first and second primary scoreboards are provided for scheduling/servicing of, for example, higher and lower priority traffic, higher and lower cell rate traffic, or externally and internally generated traffic, respectively. A bubble count is maintained for the second scoreboard, and the count is incremented each time the first scoreboard is serviced and decremented each time an idle slot is encountered on the second scoreboard but not queued for transmission. Scheduling requests for the second scoreboard are then made at a target time plus the bubble count. In the case of multiplexing external and internal cell sources, the bubble count may represent the number of cells that have been sent on a given transmission link but not scheduled in the primary scoreboard, and may be incremented each time the primary scoreboard is serviced, and decremented each time an idle slot on the primary scoreboard is encountered but not queued for transmission.

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Bellingham, MA, United States of America

Daniel J Lussier