Sun Microsystems, Inc.

Daniel J Flees

Matthew E Becker

Peter Redmond O'Brien

Eileen H You

Micah C Knapp

Chung Lau Chan

Thomas E Dillinger

In accordance with the present invention, a method, system, computer system, and computer program product for considering clock skew in designing digital systems with latch-controlled circuits are provided. The disclosure teaches a method for determining whether logic operations can be performed within the available time and allows detailed modeling of clock skew for different domains of the integrated circuit. Taking clock skew into account for each domain, worst-case timing paths can be determined for circuits controlled by either flip-flops or latches. A design of an integrated circuit can be revised or verified using the method taught. The disclosure envisions that integrated circuits, printed circuit boards, computer systems and other components will be manufactured based upon designs developed with the method taught.

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San Jose, CA, United States of America

Daniel J Flees